JPS5915230B2 - automatic phase control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used, for example, in a phase modulation type demodulation device;
The present invention relates to an automatic phase control circuit which requires less control amount per cycle and further reduces jitter of demodulated carrier waves.

An automatic phase control circuit (hereinafter referred to as an APC circuit) is used in a phase modulation type modulation/demodulation device used for data communication or the like to generate a demodulated carrier wave used for synchronous detection of a demodulator. This type of digital APC circuit normally detects whether the phase of the demodulated carrier wave is delayed or ahead of the input carrier wave, and according to the result, inserts a pulse into the high-order clock or inserts a pulse into the high-order clock. The phase is controlled by deleting pulses. The amount of phase control per pulse inserted or deleted at this time is determined by the ratio (frequency division ratio) between the frequency of the high-order pulse whose pulse is inserted or deleted and the frequency of the demodulated carrier wave. be done. On the other hand, since the jitter of the demodulated carrier wave depends on the amount of phase control per time, in order to reduce the jitter, it is necessary to increase the 15 frequency ratio by the above-mentioned amount, and the frequency of the high-order clock becomes higher. Furthermore, since pulses are inserted into the high-order clock, an original oscillation clock with a frequency three times or more of the high-order clock is required. However, there are limits to the operating frequency of the components that make up the circuit.
If it is 0, the frequency of the original oscillation clock is limited, and the frequency division ratio cannot be made sufficiently large, leading to an increase in jitter of the demodulated carrier wave. The present invention has been made in consideration of these points, and it is possible to reduce jitter by controlling the phase by using the phase shift of 25 higher-order clocks without inserting or deleting pulses. An automatic phase control circuit is provided.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an automatic phase control circuit 30 according to the present invention, except for the portion surrounded by dotted lines, which has a well-known configuration. 1a and Ib are multiplication circuits connected in parallel to the carrier wave input terminal, the output terminals of which are connected to the reception logic circuit 3 via low-pass filters 2a and 2b, and the low-pass filter 2
The output terminals of a and 2b are further connected to an absolute value comparison circuit 4, and the output terminals of this absolute value comparison circuit 4 and the output terminal of the reception logic circuit 3 are connected to a polarity determination circuit 5.

The output terminal of this polarity discrimination circuit 5 is connected to the input terminal of a phase control section 8, which will be described later. Further, the output terminal of this phase control section 8 is connected to the frequency dividing circuit 6, and the output terminal of this frequency dividing circuit 6 has a
It is connected to a 0 phase difference circuit 7, and each output terminal of this 90 phase difference circuit 7 is connected to the multiplication circuits 1a and 1b. The phase control section 8 receives the original oscillation clock D which is the output of the oscillator 9.
90 phase difference circuits 81 are provided which input the 90
The output terminal of the phase difference circuit 81 is connected to the input terminal of a channel selector 82, and the output terminal of the channel selector 82 is connected to the frequency dividing circuit 6 and also to the input terminal of the starting pulse generating circuit 83.

An original oscillation clock D and a sampling pulse S are further applied to the input of this starting pulse generating circuit 83. Further, the output terminal of the starting pulse generation circuit 83 is connected to the input terminal of an up-down counter 84, and the output terminal of this up-down counter 84 is connected to the terminal A of the channel selector 82,
Connected to B. Further, a D flip-flop circuit 85 is provided, and an input terminal D of this D flip-flop circuit 85 is provided.
is connected to the output terminal of the polarity discrimination circuit 5, and the terminal CLK
The sampling pulse S is input to the output terminal Q.
is connected to the terminal U/D of the up-down counter 84. As shown in FIG.
It is composed of a combination of flip-flop circuits 811 and 812. The starting pulse generating circuit 83 is composed of four D flip-flop circuits 831, 832, 833, 834, an inverter 835, and an AND gate 836.
Next, the operation will be explained.

As is generally known, the operating principle of the APC circuit is to control the phase of the demodulated carrier wave so that the opening of a so-called eye pattern when displayed on an oscilloscope is maximized. That is, input carrier wave A and demodulated carrier waves Bl, B2
is multiplied by the multiplication circuits 1a and 1b, and the low-pass filter 2a
, 2b to the reception logic circuit 3. The outputs of the pass filters 2a and 2b are phase detection outputs Cl and C2, and these phase detection outputs Cl and C2 are called eye patterns. The absolute values of these two eye patterns are compared by an absolute value comparison circuit 4, and the result is led to a polarity discrimination circuit 5.
The polarity is determined based on the output control signal of the reception logic circuit 3. The output of the polarity determining circuit 5 represents the lead or lag of the demodulated carrier waves B1 and B2, and this output is input to the phase control section 8. The phase control section 8 controls the phase of the high-order clock F, which is the frequency-divided output of the original oscillation clock D, by advancing or delaying it in accordance with the state of the signal Z. The output F of this phase control section 8 is frequency-divided by a frequency dividing circuit 6, and further 9
The signal passes through the 0.08 phase difference circuit 7 and becomes two demodulated carrier waves B19B2 having a phase difference of 900 degrees. Here, the operation of the phase control section 8 will be explained using the time chart shown in FIG.

The original oscillation clock D from the oscillator 9 is 90° phase difference circuit 8
1, and as a result, the phase difference circuit 81 outputs four phases E each having a phase difference of 90 degrees. ,El,E
2, yielding E3. Each of these outputs E. , El, E2, E3
are input to input terminals 0, 1, 2, and 3 of the channel selector 82. This channel selector 82 selects the above inputs, EO, E depending on the state of the binary inputs input to terminals A and B.
,,E2,E3 is selected and led to the output terminal Y. In other words, depending on the content of the phase control signal Z, the higher-order clock F
Shifts the phase of the phase in the direction of lead or lag. The states of the binary inputs A and B of the channel selector 82 are determined by an up-down counter 84, which is up/down controlled by the output H of the D flip-flop circuit 85, and is controlled by the starting pulse generating circuit. The state changes at the rising edge of the output activation pulse G at 83. D
A phase control signal Z is connected to the D terminal of the flip-flop circuit 85.
is input, and the sampling pulse S is input to the clock terminal, so the phase control signal Z is sampled at the center of the eye pattern by the sampling pulse S and stored.

This produces an output H, which has a different polarity depending on the content of the phase control signal Z, that is, whether it is in a leading or delayed state. On the other hand, the sampling pulse S1 output F of the channel selector 82 and the original oscillation clock D are input to the starting pulse generation circuit 83, and after the sampling pulse S rises, it falls at the first rise of the channel selector output F.
Thereafter, a starting pulse G that rises for one period of the original oscillation clock D is output.

That is, in FIG. 2, the D flip-flop circuit 83
Assume that the Q output of No. 4, that is, the starting pulse G, is now 1''.

Here, when the sampling pulse S rises, the σ output of the D flip-flop circuit 831 becomes 1". Then, when the output F of the channel selector 82 falls, the σ output of the D flip-flop circuit 832 becomes 1", and thereby Q output power t1 of D flip-flop circuit 833
become. At this time, the D flip-flop circuit 831
is set by the Q output o'' of the D flip-flop circuit 832, and the ζ output becomes ool. After the o output of the D flip-flop circuit 833 becomes o1'',
When the output of the channel selector 82 rises (the original oscillation clock D has already risen immediately before this), the AND gate 83
6 becomes 1'', and the D flip-flop circuit 8
The Q output of 34 falls to ゞo''. That is, the starting pulse G becomes ゞo''. As a result, the D flip-flop circuit 833 is set and its σ output is inverted to o'', so when the output of the AND gate 836 rises again at the rising edge after one period of the original oscillation clock D, the D flip-flop circuit 833 is set. The o output of the circuit 834, that is, the starting pulse G rises again to 11. On the other hand, the up-down counter 84 changes its state according to the content of the output H of the D flip-flop circuit 85 and at the timing of the starting pulse G. The outputs are input to the terminals A and B of the channel selector 82.Thereby, the channel selector 82 inputs E., El, E2, E3 according to the values of the binary inputs A and B. For example, as shown in the time chart of FIG. 3, if the content of the phase control signal Z indicates advance, the output H of the D flip-flop circuit 85 will rise at the rise of the sampling signal S. At the rising edge of the starting pulse G,
If the input E2 had been selected by the channel selector 82 until then, it is switched to the input E1 and the phase is delayed.

(Fig. 3A) Conversely, when the content of the phase control signal Z indicates a delay, the output H of the D flip-flop circuit 85 rises at the rising edge of the sampling signal S, and the channel selector 82 changes at the rising timing of the starting pulse G. The selection is switched from input E2 to input E3 to advance the phase. (Figure 3) In this way, the output of the channel selector, that is, the phase of the high-order clock F, is controlled to advance or lag in response to the delay or advance of the demodulated carrier wave. The amount of phase shift of the high-order clock F is one cycle of the original oscillation clock D, and therefore the phase control amount of the demodulated carrier wave obtained by dividing this high-order clock F by the frequency dividing circuit 6 is 1. Each cycle corresponds to one period of the original oscillation clock D. As described above, according to the present invention, the phase of a phase-controlled signal such as a demodulated carrier wave is generally controlled by dividing the original oscillation clock by n to obtain n phases, and selecting one of them to control the phase of the phase-controlled signal such as a demodulated carrier wave. Since this is achieved by shifting the high-order clock phase, the amount of phase control per time can be equal to one period of the original oscillation clock. Therefore, compared to the conventional method of performing phase control by inserting or deleting pulses, when the source oscillation clocks are equal, the amount of phase control per time is less than 1/3, and the controlled phase control with less jitter is achieved. I can get a signal. Conversely, if the amount of phase control per cycle is allowed to be the same as in the conventional system, the frequency of the original oscillation clock can be reduced to 1/3 or less. Note that the phase difference circuit and the starting pulse generation circuit are not limited to the example shown in FIG. 2, and may have other configurations.

Furthermore, the term "original oscillator clock" is used merely to mean a clock with a higher frequency than a high-order clock, and does not necessarily mean the output of the original oscillator.

[Brief explanation of drawings]

FIG. 1 is a program diagram showing an automatic phase control circuit according to an embodiment of the present invention, FIG. 2 is a program diagram showing a specific example of the main part of FIG. 1, and FIG. This is a time chart of the automatic phase control circuit shown in the figure. 1a, 1b... Multiplication circuit, 2a, 2b...
...pass filter, 3...reception logic circuit,
4... Absolute value comparison circuit, 5... Polarity discrimination circuit, 6... Frequency division circuit, 7...90
0 phase difference circuit, 8... phase control section, 9...
...Oscillator, 81...900 Phase difference circuit, 82
... Channel selector, 83 ... Start pulse generation circuit, 84 ... Up-down counter, 85, 811, 812, 813, 831, 832,
833, 834...D flip-flop circuit,
835...Inverter, 836...And gate.

Claims (1)

[Scope of Claims] 1. Means for dividing an original oscillation clock by n to obtain n clocks each having a phase difference of one period of the original oscillation clock, and a phase control that indicates the lead or lag of the phase of a phase-controlled signal. an up-down counter that is controlled up and down according to a signal; and an up-down counter into which the n clocks are input, one of which is delayed or advanced by one period of the original oscillation clock from the current output. An automatic phase control circuit comprising: a channel selector that selectively outputs an output according to the output of the channel selector; and controlling the phase of the phase controlled signal obtained from the output clock of the channel selector. 2. The timing of the up-down control of the up-down counter is made to match the timing one cycle of the original oscillation clock after the rising edge of the output clock of the current channel selector. automatic phase control circuit.