JPS5915389B2 - Manufacturing method of junction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method for reducing noise of a junction field effect transistor.

2. Description of the Related Art In recent years, demands for higher performance in electronic devices have created a need for lower noise semiconductor elements used in these devices.

0 Regarding junction field effect transistors,
Although they are advantageous in reducing noise compared to bipolar transistors, there is a need to achieve even higher levels of noise reduction.

As is well known from the principle of operation, the main noise of a junction field effect transistor is channel thermal noise, and to reduce this it is necessary to increase the mutual conductance.

However, in the current manufacturing technology, in addition to this thermal noise, generation and recombination noise caused by fluctuations in the combined current of carriers in the gate junction and so-called 1/f noise have values that cannot be ignored. Reducing these noises is a manufacturing technology issue, so the factors are complex; It has become clear that crystal defects induced during heat treatment play a major role.

The PN junction O 2 in a junction field effect transistor is a gate junction, and therefore it is important for noise reduction to suppress induced defects at the junction interface of the gate junction as much as possible and to reduce leakage current.

Here, the structure of a conventional general junction field effect transistor will be briefly explained.

FIG. 51 is a schematic cross-sectional view of its structure, in which 1 is a P-type silicon substrate, 2 is an N-type epitaxial layer, 3 is a P-type diffusion region, 4 is a P-type gate region, 5- and 6-.
are a source region and a drain region formed to be highly doped N+ type, respectively.

Although not shown in this cross-sectional view, the P-type diffusion region 3
Similar to the structure in which an island region is formed by isolation diffusion in a well-known integrated circuit, a source region and a drain region are formed in an island region 7 that surrounds a predetermined region of the epitaxial layer 2. ing. In addition, the gate region 4
It also extends in a long and narrow direction perpendicular to the plane of the paper, and extends as it is to the P-type diffusion region. Therefore, gate region 4
are also electrically connected to the substrate via the P-type diffusion layer, so the gate junction is actually at the interface between these regions and the island region 7, that is, on the island region side of the P-type diffusion layer 3. , an interface 10 between the substrate and the epitaxial layer, and a junction surface of the gate region.

Usually, an electrode is not formed directly on the gate region 4 using metal wiring, but rather on a part of the substrate 1 or the diffusion region 3, which has a relatively wide area.

Now, in such a conventional junction field effect transistor, in order to reduce the gate junction leakage current as described above, in order to suppress the occurrence of induced defects as much as possible, P
It is necessary to reduce the impurity concentration in the diffusion process of the diffusion region 3 of the mold. In other words, it is known from previous research results that the occurrence of defects induced during diffusion increases rapidly as the impurity concentration increases. However, as a result of research on reducing the noise of junction field effect transistors, the inventors found that the leakage current at the PN junction surfaces 8 and 9 on the island region side of the P-type diffusion region 3, as shown in FIG. diffusion region 3 in order to reduce, i.e. reduce induced defects in such region
It has been found that reducing the concentration of diffused impurities in the sensor has no effect on lowering the noise.

This can be understood to be due to the fact that as the diffusion concentration decreases, the series resistance at the gate electrode increases, and the thermal noise due to this series resistance increases. Therefore, unless the series resistance in this region is increased and the leakage current at the junction surface is reduced, the noise of the device cannot be reduced.

In view of these conventional problems, the present invention manufactures a junction field effect transistor having a novel structure capable of minimizing the series resistance value in the diffusion region and reducing junction leakage current in order to reduce noise. The purpose is to provide a method.

As mentioned above, when the impurity concentration in the diffusion region is increased in order to minimize the series resistance of the gate electrode, the inventors' observations using a transmission electron microscope have shown that impurity precipitation or dislocation networks occur. It was found that in severe cases, the dislocation network extended to an area extending approximately 1 micron from the junction boundary. Furthermore, it was confirmed that the presence of these dislocation networks in the close vicinity of the junction clearly increases the leakage current, and that this increase in leakage current is due to an increase in the number of recombination centers, increasing the generated recombination noise.

It was also found that precipitation due to high concentration of these dislocation networks or diffused impurities occurs in the high concentration diffusion region and grows and extends to about 1 micron around the region. An attempt was made to reduce the generated recombination current noise by creating a double diffusion layer in the low concentration region.

FIG. 2 is a cross-sectional view of a PN junction with double diffusion layers for explaining the main points of the present invention. 11 is N type 1Ω-Cm
A silicon single crystal substrate is used, and a low concentration diffusion method such as a doped oxide diffusion method is used in this predetermined region to achieve a diffusion depth of 6 microns and a surface impurity concentration of 5 x 1017 cm.
3 low concentration P type regions 12 are formed.

Next, high concentration P type regions 13 are formed on the inner surface of this low concentration P type region 12 at intervals of about 3 microns by a well-known diffusion method. When measuring the electrical characteristics of the PN diode constructed in this way, it was found that the junction leakage current was clearly higher than that of a diode in which regions 12 and 13 were formed by one diffusion, compared to a sample in which one diffusion was performed at a high concentration. , and the series resistance value in this region is clearly lower than that of the sample that was diffused once at a low concentration. That is, if the design dimensions are optimally selected, it is possible to reduce the junction leakage current while having a series resistance value of the P region that is approximately equal to that of forming 12 and 13 regions by one high concentration diffusion. This has been confirmed. This indicates that the recombination center generated in the high concentration region 13 has not reached the junction boundary, that is, the vicinity of the interface between the N type substrate 11 and the low concentration P type region. Based on these experimental facts, the present invention has developed the diffusion region of a junction field effect transistor (the region that electrically connects the substrate gate and the surface gate and serves as the electrode extraction part) to such low-concentration and high-concentration double diffusion. It is characterized by its structure in layers.

Specific embodiments of the present invention will be described with reference to the drawings. Third
The figure is a perspective sectional view when the present invention is applied to an N-channel junction field effect transistor. For ease of explanation, the symbols of components common to the conventional example are the same as in FIG. 1 is a P-type silicon substrate, 2 is an N-type epitaxial layer, 22 is a P-type low concentration diffusion region, 33 is a P-type high concentration diffusion region, 4 is a P-type gate region, 5 and 6 are each N
A source region and a drain region formed by +diffusion.

As can be seen from the figure, the PN junction is formed by the interfaces 8, 9, and 10 of the P region in contact with the N-type island region and the gate region, but the PN junction is formed by the gate region and the P-type high concentration diffusion region 33. The dislocation network is structured so that it does not reach the -C junction interfaces 8 and 9 due to the constant spacing up to the P-type low concentration diffusion region 22, and an increase in leakage current due to induced defects is avoided. Further, one ends of the gate regions 4 are connected to each other by P-type diffusion regions and reach the gate electrodes, and since one end of each of the gate regions 4 extends to the P-type high concentration diffusion region 33, the series connection Although the PN junction interfaces 8 and 9 are constituted by the P-type low concentration diffusion region 22, the resistance value does not increase.

FIG. 4 explains the manufacturing process of this example,
As shown in Figure 4a, the P-type example is a 1Ω-Cm substrate 1.
Next, an N-type epitaxial layer 2 is grown to a thickness of 35 microns at 0.5 Ω-Cm.

Next, as shown in FIG. 4B, a P-type low concentration diffusion region 22 is formed from a predetermined region of the surface of the epitaxial layer 2 to a depth reaching the substrate by a well-known low concentration selective diffusion technique. The diffusion conditions at this time are, for example, a diffusion depth of 5 microns and a surface sheet resistance value of 350 Ω/mouth. In the figure, since the surface oxide film for selective diffusion is a well-known matter, it is omitted in order to simplify the explanation. Next, as shown in FIG. 4c, a P-type high-concentration diffusion region 33 is formed inside the P-type low-concentration diffusion region 22 by a well-known selective diffusion method so as to create a gap of about 2 microns at the end of diffusion. Form.

The surface sheet resistance value in the region 33 at this time is approximately 9 Ω/mouth. In this case, regions 22 and 33 are formed using different selective diffusion masks, that is, usually by forming a silicon oxide film on the surface of the epitaxial layer and opening holes in it by photo-etching. The process may be performed twice depending on the area of the opening, or the regions 22 and 33 may be formed by using a single selective diffusion mask both times and only with a difference in heat treatment conditions. If the process is performed using a single mask, the number of steps is reduced, but it is easier to control the diffusion if the process is performed using two masks of different sizes. It is up to those skilled in the art to decide which method to use depending on the characteristics of the manufacturing process, but in the experiments conducted by the inventors, it is better to use masks with two different dimensions and to make the diffusion depth almost the same in regions 22 and 33. This was advantageous in reducing noise. FIG. 4d shows a P-type gate region 4, a source and drain region 5 formed by N+ diffusion, and
Although not shown in the drawings, electrodes are then attached using a well-known method to complete the device. As described above, in the present invention, the diffusion region connected to the substrate gate of a junction field effect transistor is constructed with a low-concentration and high-concentration double diffusion layer, and the dislocation network induced by the high concentration region is located near the PN junction. The series resistance value is low, the junction leakage current is reduced, and the noise can be reduced, which greatly contributes to improving the performance of junction field effect transistors.

[Brief explanation of the drawing]

Fig. 1 is a structural cross-sectional view of a conventional general junction field effect transistor, Fig. 2 is a cross-sectional view of a PN junction with a double diffusion layer, and Fig. 3 is a junction type according to a specific embodiment of the present invention. 4A to 4D, which are cross-sectional views of a field effect transistor, are diagrams showing the manufacturing process of the same transistor according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Epitaxial layer, 4... Gate region, 5... Source region, 6... Drain region , 22...
...Low concentration diffusion region, 33...High concentration diffusion region.

Claims (1)

[Claims] 1. A step of forming an epitaxial layer of a reflective conductivity type on one main surface of a semiconductor substrate of one conductivity type, and enclosing a predetermined region of this epitaxial layer to form an island region and depositing a layer on the substrate from the surface. a step of forming a first region with a low impurity concentration of the same conductivity type as the substrate to be reached, and a step of forming a second region of the same conductivity type with a high concentration again inside this first region. and forming a source region, a gate region connected to the second region, and a drain region in the island region, wherein the dislocation network induced by the second region is caused by the first region. A method for manufacturing a junction field effect transistor, characterized in that the PN junction does not extend to the vicinity of the PN junction formed by the PN junction.