JPS6153866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a low-noise planar transistor.

FIG. 1 is a cross-sectional view of a conventional planar transistor. The following process is used to manufacture such a transistor. An oxide film 2 such as SiO ₂ is formed on the main surface of a semiconductor substrate 1 of the first conductivity type, a window is formed in a predetermined region of this oxide film by a well-known photolithographic technique, and the oxide film 2 is used as a mask to form a window in this oxide film. Diffusion of impurities of the second conductivity type through the window
A conductive type base region 3 is formed, and then an oxide film 4 is formed on the surface of this base region 3. This oxide film 4 is generally formed at the same time as the base region 3 by high temperature thermal oxidation. Next, a window is formed in a predetermined region of the oxide film 4 on the base region 3 in the same manner as described above, and impurities of the first conductivity type are diffused through this window using the oxide film 4 as a mask to form an emitter region of the first conductivity type. form 5. Next, the emitter region 5 is formed by a vapor phase growth method or a thermal oxidation method.
After forming an oxide film 6 on the surface of the base region 3 and the emitter region 5, windows for taking out electrodes from the base region 3 and emitter region 5 are formed at predetermined portions of each region. Next, a metal such as aluminum is deposited and patterned in a well-known manner to form the base electrode 7 and the emitter electrode 8. Furthermore, a collector electrode 9 is formed on the back surface of the semiconductor substrate 1.

Transistors manufactured in this way are easy to manufacture, have high performance, and are now widely used because their junction surfaces are protected by an oxide film, resulting in stable characteristics and improved reliability. It is used. However, as is clear from the above description, the oxide film used as a mask for impurity diffusion remains on the surface of the junction and is used as a surface protection film. Since this oxide film is obtained by high-temperature heat treatment during the process, crystal defects and thermal distortion occur at the interface between the oxide film and the substrate surface due to the difference in coefficient of thermal expansion. Since such crystal defects and thermal strain cause recombination centers, conventional transistors have a much larger number of recombination centers in the surface region than in the interior. In particular, in emitter and base junctions, a high concentration of impurities is diffused when forming the emitter region, so many crystal defects such as dislocations occur near the junction, resulting in the formation of many recombination centers in this area. be done.

In addition, because the ends of the junction terminate at the surface of the semiconductor substrate, a considerable amount of carriers are injected from the junction in the surface region, making it susceptible to crystal defects on the surface and causing deterioration of transistor characteristics. There's a problem. That is, a portion of the minority carriers injected from the emitter region into the base region are captured by crystal defects and recombined, resulting in an increase in base current, lowering the current amplification factor, and deteriorating the characteristics of the transistor. Furthermore, if some of the carriers are trapped in crystal defects, the current fluctuates, causing low-frequency noise. In reliability tests, etc., surface levels caused by crystal defects are generated near the interface between the oxide film and the substrate, and carriers are captured in these levels, causing the potential on the surface of the base region to fluctuate, which also deteriorates the characteristics of the transistor. It is becoming the cause of

As described above, the conventional manufacturing method has the disadvantage that the characteristics of the semiconductor device deteriorate due to the occurrence of crystal defects.

The present invention has been made to solve these conventional drawbacks, and its purpose is to provide a method for manufacturing a semiconductor device that suppresses the occurrence of crystal defects and provides low-noise characteristics. It's about doing.

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 2 is a sectional view showing each manufacturing process of a planar transistor manufactured by an embodiment of the method for manufacturing a semiconductor device according to the present invention. As shown in FIG. 2a, a semiconductor substrate 21 made of N-type silicon
An oxide film 22 made of SiO ₂ was formed to a thickness of about 4000 to 6000 Å on the main surface of the substrate by a thermal oxidation method, and then windows were formed in predetermined areas of the oxide film 22 by patterning using a well-known method. Thereafter, a P-type base region 23 is formed by diffusing P-type impurities. In this case, the surface concentration of the base region 23 is 1×10 ¹⁸ ~
It is desirable to set it to about 5×10 ¹⁸ cm ^-3 . In addition, 2
4 is a thermal oxide film formed during diffusion of P-type impurities.

Next, as shown in FIG. 2b, the thermal oxide film 24 is patterned by a well-known method to form windows 25a,
25b is formed. It is preferable that the thickness of the thermal oxide film 24 is approximately 4,000 to 6,000 Å, similar to the oxide film 22. If the film is thicker than this, the window 25
After forming windows 25a and 25b, distortion due to the difference in coefficient of thermal expansion tends to occur around the windows 25a and 25b, causing deterioration of characteristics. Next, polycrystalline silicon 26 is deposited on the entire surface of the semiconductor substrate 21 by vapor phase growth.
is formed to a thickness of about 4000 to 6000 Å, and then an N-type impurity such as phosphorus is diffused over the entire surface to form N-type low concentration diffusion impurities 27a and 27b in the windows 25a and 25b above the base region 23, respectively. Form.
In this diffusion, it is necessary to prevent the impurity concentration from becoming high, and it is controlled to be approximately the same as or slightly higher than the concentration of the base region 23. This allows for good bonding in the base region 23. Next, polycrystalline silicon 26
An oxide film 2 made of SiO ₂ is formed on the surface of by thermal oxidation method.
8 is formed to a thickness of about 2000 to 3000 Å. FIG. 2b shows this situation.

Next, as shown in FIG.
, and a region between the low concentration diffusion impurity 27b is removed, and N type impurity is diffused at a high concentration using the oxide films 22 and 28 as a mask to form a deep emitter region 29 having a high impurity concentration. Due to the high temperature heat treatment at this time, impurities are diffused from the polycrystalline silicon 26 doped with N-type impurities,
A low impurity concentration emitter region 37a and a low impurity concentration region 37b are formed. The depths of these emitter regions 37a and low impurity concentration regions 37b are shallow because of their low impurity concentrations, but it is desirable that the depths be about 1/3 to 1/5 of the depth of emitter regions 29. Here, the impurity concentration of the emitter region 29 is set at an appropriate value since it is undesirable that it be too high from the viewpoint of device characteristics. Therefore, it is desirable that the diffusion temperature is also 1100°C or less. The reason for this is to suppress thermal strain caused by SiO ₂ near the emitter junction as much as possible. In addition, the emitter area 29
When providing a window for forming the base region 23
The upper polycrystalline silicon 26 was also removed;
This is because, when the base electrode is formed later, the base electrode and the emitter electrode may be connected using polycrystalline silicon having conductivity.

Next, as shown in FIG. 2d, after forming an SiO ₂ oxide film 30 on the surface by thermal oxidation or vapor growth, contact holes 31a and 31b are formed in the area where electrodes are to be formed by a well-known method. form.

Next, as shown in FIG. 2e, a metal such as aluminum is vapor-deposited on the surface and patterned using a well-known method to form an emitter electrode 32 in the contact hole 31a and a base electrode in the contact hole 31b. Electrodes 33 are formed respectively. At the same time, a collector electrode 34 is formed on the other main surface of the semiconductor substrate 21. In this way, a planar transistor is completed.

The transistor obtained by such a manufacturing method has two regions: a deep emitter region 29 with a high impurity concentration and a shallow emitter region 37a with a low impurity concentration formed to surround the emitter region 29, Further, a low impurity concentration region 37b is formed around the emitter region 37a at a distance d (shown in FIG. 2e) to surround it, and these regions are further formed to connect the emitter region 37a and the low impurity concentration region 37b. It has a structure in which polycrystalline silicon 26 is doped with an impurity of the same conductivity type as the region. Here, the distance d is desirably about 2 to 5 microns, and if it is larger than this, the effect will be significantly reduced, so it is important to manufacture the film so that it falls within the above range. Further, the emitter region 37a has a function of suppressing the injection of carriers into the base region 23, and as described above, it is desirable that its concentration be approximately the same as or slightly higher than the surface concentration of the base region 23. . Moreover, the emitter area 37
The depth of the junction a also needs to be shallow to about 0.5 to 1.0 μm. This is to increase the resistance of the diffusion region and suppress injection of carriers into the base region 23. Furthermore, the low impurity concentration region 37b has the function of reducing the base surface region near the emitter region, reducing the recombination area of carriers, and suppressing recombination. And low impurity concentration region 3
7b is connected to the emitter region because it has been experimentally revealed that if this region is electrically floating, the operating state characteristics become unstable.

Therefore, transistors manufactured using this method have fewer recombination centers due to crystal defects and thermal strain near the surface, and as a result, the recombination current in the surface region, especially near the emitter junction, is reduced, resulting in a small current. It becomes possible to increase the current amplification factor in the basin. Furthermore, by lowering the injection efficiency in the surface region, current fluctuations can be reduced and a low-noise transistor can be obtained.

In the above embodiments, an example was explained in which the present invention was applied to a unit transistor, but it goes without saying that the present invention can also be applied to a transistor in an integrated circuit. Further, although N-type silicon is used as the semiconductor substrate, P-type silicon may be used to make each region of the opposite conductivity type.

As described above, according to the method for manufacturing a semiconductor device according to the present invention, crystal defects near the surface can be suppressed in a simple and short process, and a semiconductor device with low noise and stable characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a planar transistor manufactured by a conventional method, and FIGS. 2 a to 2e are cross sections of a planar transistor manufactured by an embodiment of the method for manufacturing a semiconductor device according to the present invention at each manufacturing step. It is a diagram. 21... Semiconductor substrate, 22, 28, 30... Oxide film, 23... Base region, 24... Thermal oxide film,
25a, 25b... window, 26... polycrystalline silicon, 27a, 27b... low concentration diffusion impurity, 2
9, 37a... Emitter area, 31a, 31b...
...Contact hole, 32...Emitter electrode, 33...
...Base electrode, 34...Collector electrode, 37b...
...Low impurity concentration region.

Claims (1)

[Claims] 1. A step of forming a base region of the second conductivity type by diffusing an impurity of the second conductivity type into the surface of the semiconductor substrate of the first conductivity type which becomes the collector, and forming an insulating film on the surface of the base region. A process of removing the insulating film of a first part that will become an emitter region and a second part surrounding this part at a predetermined distance in the vicinity of this part; forming a silicon layer and further diffusing impurities of a first conductivity type to selectively form low concentration diffused impurities of the first conductivity type in each portion on the base region; and insulating the polycrystalline silicon layer. After forming the film, there is a step of removing the polycrystalline silicon layer and the insulating film from other parts, leaving only the peripheral part of the first part and the area between the second part and the remaining insulating film as a mask. A deep emitter region with a high impurity concentration is formed in the first part by diffusing impurities of the first conductivity type at a high concentration, and the impurities in the peripheral part of the first part and the second part are removed by heat treatment at this time. 1. A method of manufacturing a semiconductor device, comprising the step of forming low impurity concentration regions by diffusion.