JPS5915425B2 - Signal disconnection and mark rate detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal disconnection and mark rate detection circuit for detecting a signal disconnection and mark rate abnormality in a pulse signal.

In communication systems that use pulse signals such as PCM signals, in order to monitor human output signals, the presence or absence of pulse signals is detected, and if the mark rate becomes abnormally high or low, this is also detected. Therefore, a signal disconnection and mark rate detection circuit is used.

FIG. 1 is a diagram illustrating changes in the state of such a pulse signal.

In the figure, a is a repetitive signal with a mark rate of 1/m,
A repetition signal of a mark rate (1-1/m) which is an inversion of this is shown. is an eye pattern showing a random signal with a mark rate of 1 and a random signal with a mark rate (1-1) which is the inverse of this. c shows an eye pattern when an instantaneous interruption of n bits occurs in the pulse signal. Further, d indicates a case where a signal interruption occurs after a certain time using an eye pattern. FIG. 2 is a circuit diagram showing the configuration of a conventional signal disconnection and mark rate detection circuit.

In the figure, the human signal passes through OR-NOR gate 1,
One is directly applied to a comparator 5 via an integrating circuit 4 consisting of a resistor 2 and a capacitor 3, and the other is applied to a comparator 9 through an integrating circuit 8 consisting of a resistor 6 and a capacitor 7 with its sign reversed. value voltage V
It is compared with th. When the human power of either of the comparators 5 and 9 exceeds the threshold value Vth, an alarm output is generated via the OR gate 10. Resistor 2 and resistor 5 both have a value R1, capacitor 4 and capacitor 6 both have a value Cl, and therefore integration circuits 4 and 8 have equal time constants CIRI. FIG. 3 is a diagram showing the relationship between signal level and threshold voltage.

The figure shows a state in which the threshold voltage Vth is set to a level 3/4 of the "o'' level, "1" level, and center level of the signal. Therefore, the circuit of FIG. When the threshold voltage is set as shown in Figure 3, the mark rate is approximately 1/4 or less or approximately 3/4.
When the value exceeds the limit, an alarm output is generated.

On the other hand, when an instantaneous interruption occurs in the input signal as shown in FIG.
Or it becomes "1", and when the output of the integrating circuit 4 or 8 rises according to the time constant ClRl and exceeds the threshold voltage Vth, an alarm output is generated.

Similarly, when the signal is disconnected as shown in Figure 1d, the 0
When the output of the R-NOR gate 1 becomes "O" or "1" and the output of the integrating circuit 4 or 8 exceeds the threshold voltage Th, an alarm output is generated. In this way, in the circuit shown in Figure 2, the upper or lower limit of the mark rate to be detected is determined only by the setting of the threshold voltage. It was difficult to get close. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to make the limit of the mark rate to be detected very close to O or 1, and to prevent instantaneous interruptions and signal interruptions. It is an object of the present invention to provide a detection circuit which can set the detection limit separately from the mark rate detection conditions and which is simple and economical in terms of construction.

In order to achieve this object, the signal disconnection and mark rate detection circuit of the present invention includes a first integrating circuit that integrates and feeds back the output signal, and operates according to the input signal pulse to change the output state. and a flip-flop which returns to the original output state when the feedback signal of the integrating circuit exceeds a certain level, and a flip-flop having a longer time constant than the first integrating circuit connected to the output of the flip-flop. The present invention is characterized by comprising a second integrating circuit and a comparator that compares the output of the second integrating circuit with a reference voltage and generates an alarm output. Examples will be described below.

FIG. 4 is a block diagram showing the configuration of an embodiment of the three-way signal cutoff and mark rate detection circuit of the present invention.

In the figure, 11 is a flip-flop. 12 is a resistor, 13 is a capacitor, and these form an integrating circuit 14.

Similarly, 15 is a resistor, 16 is a capacitor, and these form an integrating circuit 174. 18 is a comparator.

In FIG. 4, the value of the resistor 12 is R1, the value of the capacitor 13 is C1, and therefore the time constant of the integrating circuit 14 is C,
It is Rl. Similarly, the value of the resistor 15 is R2, the value of the capacitor 16 is C2, and therefore the time constant of the integrating circuit 17 is C2R2.

FIG. 5 is a diagram showing the relationship between signal level and threshold voltage in the circuit shown in FIG. 4.

In the same figure, as in the case of Fig. 3, 3/
4 shows a state in which the threshold voltage Th is set to level 4. Hereinafter, the operation of the signal disconnection and mark rate detection circuit of the present invention shown in FIG. 4 will be explained as follows:
The case of instantaneous signal interruption and the case of signal interruption will be explained separately.

FIG. 6 is a time chart showing the operation when the mark rate changes.

In the same figure, A, b, and c indicate cases where the pulse period T of the input signal 1 is sufficiently short compared to the time constant ClRl, a case where the pulse period is close to the time constant ClRl, and a case where the pulse period T is sufficiently long. In each of these figures, 1 represents the human input signal 1, and 2 represents the integrating circuit 1.
4 receives the output signal 2 of the flip-flop 11, 3 the Q output signal 3 of the flip-flop 11, and 4 the output signal 4 of the integrating circuit 17. In FIG. 4, a human input signal 1 as shown in FIG.
When the signal Q rises, the Q output becomes "1" and the output signal 2 of the integrating circuit 14 rises.

Since the output signal 2 is connected to the set terminal C of the flip-flop 11, the level of the output signal 2 is set to the set terminal S.
When the set level is reached, flip-flop 1
1, its Q output is set to "1". Therefore, the Q output becomes "0" and the output signal 2 of the integrating circuit 14 falls.Next, at the rise of the input signal 1, the Q output becomes "1" again. ”
Then, the same operation is repeated. In this way, the human input signal 1 is input to the Q output 3, and the uncertainty level width ΔV of the set level of the set terminal S of the flip-flop 11 is connected to the integration circuit 1.
An output whose frequency is divided by a period determined by ClRl of 4 is generated. In FIG. 6a, 1, 2, 3 are such input signals 1,
The relationship between output signal 2 and output signal 3 is shown. In this case, since the charging and discharging times in the output signal 2 shown in FIG. 6 A2 are equal, the Q output signal 3 has a duty of 50 (!)
is a square wave signal.

Therefore, the level of the output signal 4 of the integrating circuit 17 is 1/2 and does not reach the level of the threshold voltage Vth, so the comparator 18 does not generate an alarm signal. The period TM of the output signal 3 in such a state is determined by the following relationship. Here, V is the voltage difference between the high level and low level of the output signal 2, and Δ is the change width of the output signal 2 in the state shown in FIG. 6 A2.

That is, .DELTA. is the uncertainty level width of the set level of the set terminal S of the flip-flop 11. Next, when the input signal 1 shown in FIG. 6b1 is input, the Q output becomes "1" due to its rising edge, and the output signal 2 starts to rise, and the set level at the set terminal S increases. When the Q output of the flip-flop 11 reaches "11", the Q output becomes "0" and the output signal 2 starts to fall.

Next, at the rising edge of input signal 1, the Q output becomes "1" again. Therefore, in this case as well, the duty of Q output signal 3 is 5.
00! ), the output signal 4 of the integrating circuit 17 does not operate the comparator 18, and no alarm output is generated. In this case, the pulse period of the input signal is determined by the time constants C and R as described above.
, so the output signal 2 reciprocates between approximately the saturation value of its charging curve and approximately zero potential.

Therefore, the period of the Q output signal 3 in this case is determined by the relationship of the following equation. When the human input signal 1 as shown in FIG. is set to ``11.''

At the same time, the Q output becomes "O" and the output signal 2 falls and is held at zero potential. Next, at the rising edge of input signal 1, the Q output becomes "1" again and the Q output becomes "O".In this case, the pulse period of the input signal is set to the time constant C as described above.
Since it is sufficiently longer than lR, the duty of the Q output signal 3 becomes higher than 50 (fl), and the level of the output signal 4 of the integrating circuit 17 rises, and when it exceeds the threshold voltage Th, the comparator 18 issues an alarm. Generates output. The critical period of the Q output signal 3 in such a state is the threshold voltage 3.
Since the duty should be 75% corresponding to /4, it is clear that it is given by the following equation.

Moreover, the limit value M of the mark rate corresponding to this is given by the following equation.

Here, TO is the input signal 1-bit pulse width.

Although the above description has been made regarding the case where the mark rate decreases, the operation is the same even when the mark rate increases. Therefore, the limit value of the mark rate in this case can be determined directly from the following equation based on the relationship of equation (4). FIG. 7 is a time chart showing the operation when a momentary signal interruption occurs.

In the figure, A and b indicate the case where an instantaneous interruption of time Ti occurs in the input signal of pulse period T, and a represents the instantaneous interruption time T.
This is the case where i has a value close to the time constant ClRl but sufficiently shorter than the time constant C2R2, and b is the case where the instantaneous interruption time Tl is the time constant C
This is a case where the value is close to 2R2 and is therefore sufficiently longer than the time constant ClRl. In each figure, 1 represents input signal 1,
2 indicates the output signal 2 of the integrating circuit 14, 3 indicates the Q output signal 3 of the flip-flop 11, and 4 indicates the output signal 4 of the integrating circuit 17. When the input signal 1 shown in FIG. 7 a1 is input, the operation before the instantaneous interruption occurs is
This is no different from the case in Figure a. When an instantaneous interruption occurs and the input signal 1 becomes ゜゛01, the Q output becomes "0" and the output signal 2 of the integrating circuit 14 continues to fall, and the instantaneous interruption is resolved and the input signal 1 is input again. At this time, the Q output becomes "1" and the output signal 2 begins to rise. On the other hand, the Q output signal 3 maintains the state of "1" after the instantaneous interruption occurs, and becomes "0" when the instantaneous interruption is resolved.Since the instantaneous interruption time Ti is close to the time constant ClR, the output signal 2 is at almost zero potential. When the instantaneous interruption is resolved, it rises and reaches the set level at terminal S again.At this time, the rising time and falling time are equal, and the duty of Q output signal 3 is 50% (Fig. 7 A2, 3). Therefore, the level of the output signal 4 of the integrating circuit 17 remains at 172, and the comparator 18 does not generate an alarm output (A4 in FIG. 7).
When input signal 1 as shown in Figure b1 is input,
While the momentary interruption continues, the output signal 2 of the integrating circuit 14 falls and maintains zero potential, and rises again when the momentary interruption is resolved.

During this period, the Q output signal 3 maintains the state of "1". Therefore, the duty of the output signal 3 increases, and the level of the output signal 4 of the integrating circuit 17 rises. When Vth is exceeded, the comparator 18 generates an alarm output. In this case, the limit time Ts is the time for the output signal 4 to rise from 1/2 to 3/4, and is determined by the following equation. Ts: 0 .7C2R2,Ts+Ti(
6) FIG. 8 is a time chart showing the operation when a signal disconnection occurs.

In the figure, 1 is the input signal 1, 2 is the output signal 2 of the integrating circuit 14, and 3 is the Q output signal 3 of the flip-flop 11.
4 indicates the output signal 4 of the integrating circuit 17. 8th
When input signal 1 as shown in FIG. 1 is input, the operation before the disconnection occurs is the same as in the case of FIG. 6a.

When the input signal is disconnected, the output signal 2 falls and reaches zero potential. On the other hand, the Q output signal 3 maintains the state of "1", and the level of the output signal 4 of the integrating circuit 17 continues to rise and exceeds the threshold voltage Th. This causes the comparator 18 to generate an alarm output. In this case, the signal disconnection detection time is (6
) is the same as the limit time in the case of instantaneous interruption shown in formula. In this manner, the signal interruption and mark rate detection circuit of the present invention can detect any of the cases of a change in mark rate, a momentary signal interruption, and a signal interruption, and generate an alarm output.

In this case, the mark rate limit value can be determined separately by the time constant ClRl, and the signal interruption and signal interruption limit values can be determined separately by the time constant C2R2. As explained above, according to the signal interruption and mark rate detection circuit of Mokura's invention, it is possible to detect the limit of the mark rate very close to O or 1 with a simple configuration, and it is also possible to detect instantaneous signal interruptions and signal interruptions. This is extremely effective because the detection limit in the case of 1 can be determined separately from the detection limit for mark rate changes.

[Brief explanation of drawings]

Fig. 4 is a diagram explaining changes in the state of a pulse signal, Fig. 2 is a circuit diagram showing the configuration of a conventional signal disconnection and mark rate detection circuit, and Fig. 3 shows the relationship between signal level and threshold voltage. 4 is a circuit diagram showing the configuration of an embodiment of the signal disconnection and mark rate detection circuit of the present invention, and FIG. 5 is a diagram showing the relationship between the signal level and the threshold voltage in the circuit of FIG.
Figure 6 is a time chart showing the operation when the mark rate changes, Figure 7 is a time chart showing the operation when a momentary signal interruption occurs, and Figure 8 is a time chart showing the operation when a signal interruption occurs. It's a chat. 1...0R-NOR gate, 2...Resistor, 3...Capacitor, 4...Integrator circuit, 5...Comparator, 6 ...Resistor, 7...Capacitor, 8...Integrator circuit, 9...Comparator, 10...0R
Gate, 11...Flip-flop, 12...
...Resistor, 13...Capacitor, 14...
...Integrator circuit, 15...Resistor, 16...
...Capacitor, 17...Integrator circuit, 18.
·····comparator.

Claims (1)

[Claims] 1 A first integrating circuit that integrates and feeds back an output signal is operated by input signal pulses to change the output state, and when the feedback signal of the integrating circuit exceeds a certain level, the output state returns to the original state. a reset flip-flop; a second integrating circuit connected to the output of the flip-flop and having a longer time constant than the first integrating circuit; and comparing the output of the second integrating circuit with a reference voltage to generate an alarm. A signal disconnection and mark rate detection circuit comprising a comparator that generates an output.