JP3124396B2 - DC voltage fluctuation detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for determining whether a slowly varying DC voltage value of a battery which deteriorates very slowly or a charger which charges a battery very slowly exceeds or exceeds a standard value. The present invention relates to a DC voltage fluctuation detection circuit for detecting an error and generating an alarm.

In this type of detection circuit, the standard value is still attained due to a temperature change when approaching the detection voltage value, chattering due to poor contact of the connection terminal, and rather rapid level fluctuation due to external noise and the like. In many cases, an alarm is issued or a warning is intermittently violently. As a general measure to prevent this, a method of connecting an integrating circuit (or an integrator or a smoothing circuit) using a capacitor and a resistor in a preceding stage has been widely adopted.

[0003] However, according to this method, rapid level fluctuation is absorbed, but on the contrary, there is a problem that an alarm is not easily generated even though the standard value is already broken.

[0004]

2. Description of the Related Art A conventional technique will be described below. The slowly varying DC voltage is used as one input of the "comparator".
It is well known that the other input is used as a reference voltage to detect a change in the DC voltage with respect to the reference voltage by a binary output such as "H" and "L". Further, it is also known that the operation of the comparator is provided with a "hysteresis characteristic" so that a gradual change in input does not cause a sharp change in output.

FIG. 5 is a circuit diagram according to the prior art in which an integrator is connected in front of a comparator forming a DC voltage fluctuation detecting circuit. In the figure, 1 is a comparator composed mainly of the operational amplifier OP and a reference voltage source V _R, 2 is a capacitor C resistance R
And an integrator consisting of In FIG. 5, X is a DC input voltage, Xδ is an output voltage of the integrator 2, and Y is a comparator 1
The output voltage of is shown. The reason why the integrator is connected before the comparator is as described in the section of [Industrial Applications].

[0006] Figure 6 is a time chart showing the relationship between the slow fluctuation level fluctuation of the DC voltage input X and the detection output signal Y in the circuit of FIG. 5, as an example, gradual slow variation DC voltage in the vicinity reference voltage V _R When it descends, the input is interrupted (chattering) based on poor connection of the connection terminal,
This shows a case where a level fluctuation due to external noise or the like is superimposed. In the figure, the M portion indicates chattering based on poor contact of the connection terminal, the N portion indicates level fluctuation due to superimposed external noise, and the dotted line Xδ indicates the output voltage of the integrator 2.

As shown in FIG. 6, first, in the M section, the integrator output voltage Xδ is reduced by the reference voltage V due to chattering.
_The pulsation which falls below _R and rises above VR is repeated. Therefore, pulses such as Y ₁ and Y ₂ are generated at the output of the comparator, and when connected to the alarm circuit,
X intermittently alerts when X has not yet broken V _R.

[0008] In the present specification, Xderuta low voltage level of V _R is greater than the time Y, i.e. Y = "L", X
δ is higher voltage level of V _R is less than the time Y, i.e. is described for the case of Y = "H", of course may be vice versa. Therefore, in [Claims], the first
The expressions "voltage level signal" J "and second voltage level signal" K "are used.

[0009] X is truly equal to or less than V _R, of course pulse Y
₃ occurs and continues for a long time. However, in part N, Xδ
Rises and falls again due to extraneous noise, and the narrow pulse Y
_4, Y ₅ is generated. Thereafter, when Xδ further decreases, the influence of chattering and external noise decreases, and a continuous pulse Y ₆ is output.

Under the above situation, each pulse Y ₁ ,
..., alarm voltage drop is generated every time the Y ₆ is generated, and thus confusing. In order to solve such a problem, it is necessary to increase the values of R and C in the integrator 2.

[0011]

However, it is known that the operation is not sufficient when using only the "comparator" described at the beginning of the prior art. If an integrator is connected before the comparator and the values of R and C are increased as described above, a new problem occurs.

FIG. 7 is a time chart showing the relationship between the level variation of the slowly varying DC voltage input X and the detection output signal Y when the values of R and C in FIG. 5 are increased. In the figure, dotted Xderuta represents the output voltage of the integrator 2, the point P and point Q, the point X is and excess points dividing each V _R, also points Pδ and point Qδ are Xderuta is V _R Indicates the points at which it is divided and exceeded, respectively. The M part and the N part are the same as those described in FIG.

As shown in the figure, by increasing the values of R and C, the intermittent operation of alarms in the M section and the N section can be prevented, but the response speed of Xδ to X becomes slow, and X increases V _R. when divided, alarm occurs tau ₁ of delay before starting the operation, also when X exceeds the V _R, alarm occurs the tau ₂ delay before stopping the operation, causing an accident .

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a DC voltage fluctuation detecting circuit which is stable and reliable in the vicinity of a reference voltage value without an integrator, except for the above-mentioned disadvantages of the prior art. .

[0015]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a comparator, and 3 is a fluctuation check block. In the fluctuation check block 3, 4 is a timing pulse generator, 5 is a counter, 6 is a first latch circuit,
7, a reset circuit; and 8, a second latch circuit.

Now, in order to achieve the above-mentioned object, the present invention has the following configuration as shown in FIG. That is, a DC voltage that slowly changes is set as a first input and a reference voltage is set as a second input. When the DC voltage is higher than the reference voltage, the first input is used.
A DC voltage fluctuation detection circuit comprising a comparator which outputs a signal "J" at the voltage level and a signal "K" at the second voltage level when the signal is low and supplies the signal to the load. Is connected to a timing pulse generator 4 for generating a timing pulse, a counter 5 for counting with the timing pulse, and an output signal "J" or "J" of the comparator. A first latch circuit 6 which receives and latches "K" with the timing pulse, and the output signal of the first latch circuit 6 is changed from the output signal "J" or "K" at the time of the immediately preceding timing pulse to "K". And a reset circuit 7 for resetting the counter 5 by the timing pulse at the time when the counter 5 changes to "J". The number of said timing pulses latched signal "J" or the output of the first latch circuit 6 by the overflow pulse counting after outputting "K" output to a; and a second latch circuit 8 supplies the load was.

[0017]

FIG. 2 is a time chart showing signal waveforms at points indicated by corresponding reference numerals in FIG. 1 showing the principle blocks of the present invention. However, _CT is counter 5
The internal count operation is shown.

The operation will be described below with reference to FIGS. 1 and 2. The timing pulse generator 4 generates a timing pulse T having a fixed period and supplies the same to the counter 5, the reset circuit 7, and the first latch circuit 6.
From the input point Y, an output signal “Y” of the comparator 2 whose voltage level is either “L” or “H” is applied and applied to the first latch circuit 6.

At the output L ₁ of the first latch circuit 6, a signal L ₁ having the same voltage level as the input signal latched by the timing pulse T appears and is applied to the reset circuit 7 and the second latch circuit 8. . The reset circuit 7 generates a reset pulse every time the voltage level of the input signal L ₁ changes to “L” or “H”, and resets the counter 5.

[0020] The counter 5, C _T unless it is reset
As shown in FIG. 2, the ascending count operation by the timing pulse is continuously performed, and the preset number (8 in the example of FIG.
It has become. When counting the timing pulses) to the second latch circuit 8 outputs the overflow pulse L ₂ hereinafter, but repeated resume operation to increase the count from 1 to return when it is reset each time count to zero. The second latch circuit 8, also applied the output signal L ₁ of the first latch circuit 6 does not perform a latch operation as long as the pulse L ₂ overflowing from the counter 5 is not applied, the pulse L ₂ overflowing from the counter 5 , The latch operation is started immediately, and a detection signal “Z” having the same voltage level as the output signal L ₁ of the first latch circuit 6 (in the case of FIG. 2) is sent from the output point Z.

As a result, even if the voltage level of the input signal pulsates like Y ₈ , Y ₉ , and Y ₁₀ , the detection signal Z is not transmitted unless their duration is long like Y ₁₁ . Therefore, even when an alarm circuit is connected to the output point Z, a stable and reliable DC voltage fluctuation detection circuit can be realized.

[0022] Here, from the time when a long pulse duration is applied as Y _11, the transmission of the detection signal Z is defined as change confirmation time the time until the start, change confirmation time, the timing It is obvious that the product is the product of the pulse period and the number of timing pulses counted until the counter 5 outputs the overflow pulse.

[0023]

FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a comparator described in the section of [Prior Art], and reference numeral 10 denotes a fluctuation checker according to the present invention. In the fluctuation checker 10, 11 is a sampling timer, 12 is a counter, 13 is a latch circuit A, 14 is a latch circuit B, 1
5 is an exclusive OR gate, and 16 is a latch circuit C.

FIG. 1 and FIG. 1 showing the basic blocks of the present invention.
The relationship is as follows. That is, the fluctuation confirmation device 10 in FIG. 3 corresponds to the fluctuation confirmation block 3 in FIG. 1, the sampling timer 11 in the fluctuation confirmation device 10 corresponds to the timing pulse generator 4 in the fluctuation confirmation block 3, The counter 12 corresponds to the counter 5, the latch circuit A13 corresponds to the first latch circuit 6, and the latch circuit C16 corresponds to the second latch circuit 8, respectively. The latch circuit B14 and the exclusive OR gate 15 correspond to the reset circuit 7.

FIG. 4 is a time chart showing signal waveforms at points indicated by corresponding reference numerals in FIG.
Here, r indicates a reset pulse inside the counter 12.

The operation of this embodiment will be described below with reference to FIGS. 3 and 4. sampling·
The timer 11 generates a sampling pulse s, and outputs the sampling pulse s to the counter 12, the latch circuit B14, and the latch circuit A13.
And supply. The period of the sampling pulse s is set so that the fluctuation confirmation time defined in the section of [Action] is about 1 second.

The slow variation DC voltage X is input point X is input, eventually dividing the reference voltage V _R. X is the signal voltage level Y at the output point Y of the comparator 1 and dividing V _R is starts to "L" to "H". Since there is no superimposition of external noise in the section E, the voltage level X is relatively stable, and the voltage level Y is also Y ₁₂
The state of "H" is maintained for a long time as shown in FIG. However, in the F section, external noise is superimposed and X pulsates, often resulting in V _R
, The voltage level Y also repeats intermittently like Y ₁₃ and Y ₁₄ .

When the voltage level Y applied to the input of the latch circuit A13 changes to "H", the delay is delayed by a very short time φ from the rising of the sampling pulse s applied to the latch circuit A13 immediately after that point. At the time, the latch circuit A
Also, the output voltage level a of 13 turns to “H”. That is,
“H” is latched. When the voltage level Y applied to the input of the latch circuit A13 changes to "L", the latch is performed at a point in time that is delayed by a very short time [phi] from the rise of the sampling pulse s applied to the latch circuit A13 immediately after that point. The output voltage level a of the circuit A13 also changes to "L".

On the other hand, the output a of the latch circuit A13 is applied to a latch circuit B14 and a latch circuit C16. When the voltage level “a” applied to the input changes to “H”, the latch circuit B14 immediately after that point in time,
Than the rising of the sampling pulse s applied to
The output voltage level b of the latch circuit B14 also changes to "H" at the point of time when the delay is delayed by the minute time φ. Similarly, the latch circuit B1
4 changes to "L", the output of the latch circuit B14 is delayed by a very short time .phi. From the rising edge of the sampling pulse s applied to the latch circuit B14 immediately after that point. The voltage level b also changes to "L". That is, the output voltage level b of the latch circuit B14 follows the output voltage level a of the latch circuit A13 with a delay of one sampling pulse s.

Output a of latch circuit A13 and latch circuit B
Since the output b of the latch circuit A13 is applied to both inputs of the exclusive OR gate 15, when the output voltage level a of the latch circuit A13 changes to "H" or "L", the sampling pulse s is changed from the change. The pulse of the voltage level "H" is always sent from the output c of the exclusive OR gate 15 during one cycle of the period. The output pulse c of the exclusive OR gate 15 is slightly shaped inside the counter 12 and then resets the counter 12 as a reset pulse r.

The counter 12 continuously counts up by a sampling pulse unless it is reset. When the counter 12 counts a predetermined number of sampling pulses, it outputs an overflow pulse t and outputs the overflow pulse t.
, The count is reset to 0 each time it is reset, and the operation of restarting the ascending count from 1 is repeated.

The sampling pulse count number until the above-mentioned overflow pulse is output is set so that the fluctuation confirmation time is about 1 second as described above. The latch circuit C16 does not perform the latch operation even when the output signal a of the latch circuit A13 is applied unless the overflow pulse t from the counter 12 is applied. However, the latch circuit C16 immediately performs the latch operation when the overflow pulse t from the counter 12 is applied. Then, the detection signal “Z” having the same voltage level as the output signal “a” of the latch circuit A13 is transmitted from the output point Z.

As a result, the voltage level of the input signal X becomes F
Also it pulsates as parts, the detection signal Z is not sent unless their duration is not longer as Y _12. Therefore, even when the alarm circuit is connected to the output point Z, the sound does not intermittently sound.

Although the circuit of this embodiment is assembled with individual parts and individual devices, it is of course possible to incorporate it into an integrated circuit, in which case there is an excellent effect on miniaturization of the apparatus.

[0035]

As described above, according to the present invention, without providing an integrator in front of a comparator, a fluctuation confirmation block is connected in the subsequent stage, thereby preventing chattering near the reference voltage of the comparator. It is possible to realize a stable and reliable DC voltage fluctuation detection circuit that does not respond sensitively to external noise and has stable operation.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a waveform diagram at each point in the block diagram of FIG. 1;

FIG. 3 is a block diagram of an embodiment of the present invention.

FIG. 4 is a waveform chart at each point in the block of FIG. 3;

FIG. 5 is a circuit diagram of a conventional technique.

FIG. 6 is a waveform chart at each point in the circuit of FIG. 5;

FIG. 7 is a waveform diagram of FIG. 6 when R and C are increased.

[Explanation of symbols]

 Reference Signs List 1 comparator 3 fluctuation check block 4 timing pulse generator 5 counter 6 first latch circuit 7 reset circuit 8 second latch circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-63-309873 (JP, A) JP-A-63-37710 (JP, A) JP-A-58-186218 (JP, A) JP-A-56-186 169929 (JP, A) Japanese Utility Model 1-146167 (JP, U) Japanese Utility Model 1987-96580 (JP, U)

Claims (1)

(57) [Claims] 1. A slowly input DC voltage is supplied to a first input,
A reference voltage is used as a second input. When the DC voltage is higher than the reference voltage, a signal "J" of a first voltage level is output, and when the DC voltage is lower than the reference voltage, a signal "K" of a second voltage level is output and supplied to a load. In a DC voltage fluctuation detection circuit comprising a comparator, a fluctuation confirmation block (3) is connected between the comparator and the load, and the fluctuation confirmation block (3) generates a timing pulse for generating a timing pulse. Device (4) and a counter (5) for counting with the timing pulse
A first latch circuit (6) for receiving the output signal “J” or “K” of the comparator and latching the same with the timing pulse; and an output signal of the first latch circuit (6), A reset circuit (7) for resetting the counter (5) by the timing pulse when the output signal changes from "J" or "K" to "K" or "J" at the time of the timing pulse; ) Latches the output of the first latch circuit (6) by an overflow pulse that is output after counting a predetermined number of the timing pulses, and outputs a signal "J" or "K" to supply it to a load. And a circuit (8).