JPS5917538B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a high-density MOSI
In order to realize self-alignment of contacts and flattening of the surface in C, etc., a thin polycrystalline silicon layer is left in the area excluding the contact area and polycrystalline silicon wiring, and the thin polycrystalline silicon layer is oxidized. In doing so, the aim is to reduce non-uniformity in the thickness of the thin polycrystalline silicon layer, and to eliminate any remaining portions of the thin polycrystalline silicon layer that are not oxidized due to the non-uniformity of the thickness.

Conventionally, as a method of achieving self-alignment of contacts and flattening of the surface in MOSICs, etc., for example, as in Japanese Patent Application No. 50-36588, a silicon nitride film is formed on a polycrystalline silicon layer. Then, a part of the silicon nitride film and the polycrystalline silicon layer is etched to form a thin polycrystalline silicon layer in that part.The thin polycrystalline silicon layer is oxidized to become an oxide film, thereby improving the surface of the polycrystalline silicon layer. A method is known in which the silicon nitride film is removed after planarization and oxidation to obtain a self-aligned contact. The problem here is that even if the field oxide film is formed by a selective oxidation method or the like, as schematically shown in FIG. This causes what is called a step. For example, the buried field oxide film 12 is 7500A.

Therefore, the height of the part head 11 is about 2500A.

If there is such a step, the polycrystalline silicon layer 14 may be removed using a thermal decomposition method such as silane (e.g., 5650°C, 5% SiH4).
/95%N2), the polycrystalline silicon layer 1 is deposited at the stepped portion of the part head 11 as shown in FIG.
4 is deposited and bulges with approximately the same thickness in the lateral direction. Next, as shown in FIG. 1b, when thinning a part of the polycrystalline silicon layer 14, the polycrystalline silicon is etched almost vertically by, for example, reactive sputter etching in a CF4 gas atmosphere. In this case, since the polycrystalline silicon layer 14 is etched by the same amount in the vertical direction, the thin polycrystalline silicon layer 14' consists of the thin part tl and the slightly thicker part left at the step part 2, as shown in FIG. will have the following. When this thinned polycrystalline silicon layer 14' is oxidized, extra heat treatment is required to oxidize the thick portion T2, and at this time, the silicon layer used as the wiring is also oxidized more than necessary, causing the thickness of the wiring portion to be reduced. It becomes thinner, which is not desirable. Furthermore, if etching is performed that is not very directional, such as chemical etching, the gate electrode etc. will be side-etched, making it difficult to accurately form a minute gate length. Therefore, if a thin polycrystalline silicon layer 14'' as shown in FIG. 2 can be deposited, the thickness of the polycrystalline silicon will be substantially uniform even if there are steps such as the part head 11.Hereinafter, one embodiment of the present invention will be described. An example will be explained based on the drawings.In this embodiment, the process of manufacturing an n-channel silicon gate MOS transistor shown in FIG. 3a-1 will be considered.

In FIG. 3 AVc 21 is a P-type silicon semiconductor substrate.

First, a silicon nitride film 22, which is an oxidation-resistant film, is formed on the semiconductor substrate 21 to a thickness of approximately 1000λ by CVD using SiH4 and NH.The silicon nitride film 22j, which will become the field part, is coated with a photosensitive resin as a mask. The pattern is etched by removing unnecessary parts of the resin and using it as a mask to open the window (
(Hereinafter, the process of forming a pattern that will become a mask using a photosensitive resin will be referred to as a photolithography process). Next, the semiconductor substrate 2 is coated using the silicon nitride film 22 with the window opened as a mask.
1 is etched by approximately 3600A as shown in FIG. 3a. Next, the silicon is oxidized in wet oxygen to form a field oxide film 23 with a thickness of about 7500 Å. At this time, the so-called part head 231 has a thickness of about 2 to 2 mm, as shown in FIG. 3b.
It is formed with a height of 500A.

Next, the silicon nightland film 22 is removed and further oxidized to form a gate oxide film 24. At this time, the gate oxide film 23 has a substantially flat height, but there is a step difference of about 2500 A between the part and the head 231.

Next, a photolithography process is performed to open windows at locations that are to become source and drain contacts, and the gate oxide film 24 is etched to form windows 25. At this time, a portion of the gate oxide film 24 larger than the portion that will become the gate is left. Next, a first polycrystalline silicon layer 27 is grown to a thickness of about 1500 Å on the entire surface of the CVc shown in FIG. 3 by thermal decomposition of SiH4.

The first polycrystalline silicon layer 27 is grown by doping n-type impurities in advance, but of course the impurities may be diffused after growth. 31 indicates an n-type diffusion layer.

Next, a CVD oxide film 28 is formed to a thickness of about 1000 Å over the entire surface. At this time, the polycrystalline silicon layer 27 may be partially oxidized to form an oxide film. And photorin process and etching 1
From this, windows 29 and 30 are formed as shown in FIG. 3c.
Next, in FIG. 3d, a second polycrystalline silicon layer 3 is applied over the entire surface.
2 is grown to a thickness of about 2500 Å by doping with n-type impurities, then a silicon nitride film 33 is grown to a thickness of 1000 Å on the entire surface, and a CVD oxide film 34 is further grown to a thickness of about 3000 Å on the entire surface.

Next, the CVD film 3 is formed by a photolithography process (Fig. 3EK).
Using this CVD oxide film 34 as a mask, the silicon nitrite film 33 is etched with hot phosphoric acid.

Next, using the etched CVD oxide film 34 and silicon nitride film 33 as a mask, the second polycrystalline silicon layer 32 is etched by reactive sputter etching in a gas atmosphere containing fluorinated hydrocarbon CF2C. In the reactive sputter etching, the pressure of halogenated hydrocarbon CF2C is 0.1T0rΔ high frequency power 4
Under the condition of 00W, the etching rate of various films was approximately 2300A/Min. for the polycrystalline silicon film 32. ．．
Approximately 200A/Minl for CVD oxide film 34
Approximately 500A/ for silicon nitride film 33
Since it was warm at Min, I used C as a stopper for etching.
The VD oxide film 28 can be used sufficiently.

At this time, if the polycrystalline silicon 32 is over-etched by about 1.5 times, the polycrystalline silicon 32 in the part head portion can be completely etched without affecting the first polycrystalline silicon layer 27. There will be less side sex. The polycrystalline silicon layers 322 and 323 form the windows 29.
, 30 is connected to the first polycrystalline silicon layer 27. Next, in FIG.
The film 28 is etched and phosphorus ions P÷ are implanted by an ion implantation method.

At this time, in order to form the source and drain regions 35 and 36, an appropriate acceleration voltage is selected so that phosphorus ions P+ are implanted through the first polycrystalline silicon film 27 and the gate oxide film 24, but not into the gate region. In this case, for example, at an accelerating voltage of 250KV, ~2×1014at0me/
Perform under the conditions of d. Next, the CVD oxide film 34 is removed in FIG.
Silicon nitride film 33 other than 1,332,333
is selectively removed by photolithography and etching.

Next, the exposed portion of the first polycrystalline silicon layer 27 is converted into an oxide film by an oxidation process,
At the same time, the exposed portion of the second polycrystalline silicon layer 32
An oxide film is formed on the surface. At this time, the first diffusion layer 311 made of polycrystalline silicon and the diffusion layer 351 formed by ion implantation
, 361 are formed. Next, as shown in FIG. 3, the remaining silicon nitride films 331, 332, and 333 are selectively removed to expose the contact areas with the metal wiring, and aluminum is deposited using a photolithography process and etching to form the electrode wiring. form 37.

As described above, according to the present invention, since the insulating layer formed on the first semiconductor layer plays the role of a stopper, it is possible to achieve self-alignment of contacts and flattening of the surface, which are necessary for high density 1C. It is possible to reduce non-uniformity in the thickness of a thin semiconductor layer formed to reduce the step difference between semiconductor layers, which is sometimes a problem, and therefore, when it is oxidized, there is no part left unoxidized. .

In order to achieve high density, it is necessary to use minute dimensions, and for this purpose it is necessary to reduce the height difference.
According to the present invention, it is possible to reduce the non-uniformity in the thickness of the semiconductor layer due to the step near the part head, which has been a problem in the past, and it is therefore possible to accurately realize a micro-dimensional pattern with less side etching.

[Brief explanation of drawings]

Figures 1a-c are partial schematic diagrams of the manufacturing process of a conventional semiconductor device, where a is a cross-sectional view when polycrystalline silicon is deposited, and b is a perspective view when the deposited polycrystalline silicon is partially thinned. Fig. 2 is a schematic diagram of thin polycrystalline silicon deposited uniformly when there is a step on the surface; Fig. 3 a-1 is an embodiment of the present invention. MO showing examples
FIG. 3 is a cross-sectional view of the manufacturing process of the S transistor. 21... Semiconductor substrate, 23... Field oxide film, 231... Part head, 24...
...Gate oxide film, 27...First polycrystalline silicon layer, 28...CVD oxide film, 32.
...Second polycrystalline silicon layer, 33...
Silicon nitride film, 34...CVD oxide film.

Claims (1)

[Claims] 1. A first semiconductor layer with low resistivity is provided on one principal surface of a semiconductor substrate, an insulating layer with a partially opened window is formed thereon, and a second semiconductor layer with low resistivity is further formed on top of that. a step of forming a laminated film, a step of providing a conversion-resistant film on the laminated film as a mask when converting the first semiconductor layer into an insulating layer, and selectively removing a predetermined portion of the conversion-resistant film. a step of selectively removing a predetermined portion of the second semiconductor layer corresponding to the predetermined location using the insulating layer as an etching stopper; and a step of selectively removing the insulating layer exposed at the predetermined portion. and converting at least a portion of the first semiconductor layer into an insulating layer through a predetermined portion of the selectively removed second semiconductor layer, and removing the conversion-resistant film. A method for manufacturing a featured semiconductor device.