JPS5917571B2 - Pulse detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse detection circuit for detecting the presence or absence of a stuff pulse in a destuff circuit of a PCM multiplex converter.

When multiplexing PCM signals, stuff pulses are inserted depending on the difference in frequency of input PCM signals.

When the signals multiplexed in this manner are separated on the receiving side, it is necessary to perform an operation to remove the inserted stuff pulses, that is, a destuffing operation, and for this purpose, a destuffing circuit is provided on the receiving side. In such a destatuf circuit, in order to perform destatuf operation,
Received signal: It is necessary to detect the presence or absence of stuff pulses in the received signal, which requires a pulse detection circuit.
FIG. 1 is a circuit diagram showing the configuration of a conventional pulse detection circuit. In the figure, 1 is a battery, 2 and 3 are D-type flip-flops (D-F-F), 4 is an affixed gate, 5 is a PCM signal input terminal, 6 is a sampling clock pulse input terminal, 7 is a reset pulse input terminal, 8 is the output terminal of AND gate 4, 9 is the output terminal of P)-F-F2, 1
0 is the destaft output terminal. 5 Also, Figure 2 is
5 is a time chart showing signals of various parts in the pulse detection circuit shown in the figure.

In the figure, a is the input PCM signal, is the sampling clock pulse, c is the reset pulse, d is the output signal of AND gate 4, e is the output signal of D-F-F2, and Of is the destuff output signal, respectively. ing. In FIG. 1, the multiplexed PCM signal is input to terminal 5.
FIG. 2a shows a multiplexed input PCM signal, which includes three stuff pulses in one frame, indicated by notches. On the 5- side, a sampling clock pulse (Fig. 2b) indicating the insertion position of the stuff pulse in the multiplexed PCM signal is applied to the terminal 6, so that the AND gate 4 detects the stuff pulse. Then, a pulse is outputted to the output terminal 8.

00 In FIG. 2, d indicates the output signal of the AND gate 4 which generates the stuff pulse.

D-F-F2 has the output signal of the acid gate 4 applied to its clock terminal CLK, and every time the output signal pulse of the AND gate 4 is inputted, the logic state of the battery 1 applied to its D terminal is changed. It reads a level equivalent to ``1'' and outputs ``1'' to terminal 9, which is the Q output (Fig. 2e).

;The output signal of 0-D-F-F2 is applied to the D terminal of D-F-F3, and the output state of D-F-F2 is read every time the output signal pulse of AND gate 4 is input. ,
"1" is output to the terminal 10 which is the Q output (FIG. 2f).

Therefore, the destuff output signal which is the output of the terminal 10 becomes 1'' at the beginning when two or more stuff pulses are included in the multiplexed PCM signal shown in FIG. A destaft operation is performed in a destaft circuit (not shown), i.e., 3 bits 1
When two or more bits of a set of stuff pulses are "11", it is determined that the data is stuffed, and destuffing is performed. c) are respectively applied to the clear terminal CLE and reset at the end of every frame.

Therefore, the detected stuff pulses are D-F-F2 and D-
A destuff output signal is generated by a 2 out of 3 majority decision by F-F3. The destuff output signal is used for the aforementioned destuffing operation in a destuffing circuit (not shown). The reason why the pulse detection circuit shown in FIG. 1 performs a majority decision on the detected stuff pulses is that when one stuff pulse in the multiplexed signal is lost due to a code error in the line, This is to avoid a situation where the number of bits of the PCM signal on the lower-order group side increases and synchronization occurs on the lower-order group side, since the de-stuff is not performed by determining that there is no signal. In the pulse detection circuit shown in FIG. 1, AND gate 4 is used to extract the stuff pulse, so the pulse width of the sampling clock pulse at terminal 6 is
The pulse width of the multiplexed PCM signal must be narrower than the 1-bit pulse width of the multiplexed PCM signal.

In addition, Figure 1 describes the case where the number of multiplexes is 1, but when the number of multiplexes increases, an equal number of sampling clock pulse sequences are also required, which increases the scale of the circuit and wiring. Become. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to avoid restrictions on the pulse width of the sampling clock pulse, and to improve circuit and circuit performance even when the number of multiplexing increases. An object of the present invention is to provide a circuit in which the scale of wiring does not increase much.

To achieve this objective, the pulse detection circuit of the present invention includes a plurality of first D-type flip-flops connected in cascade to respond to constant period pulses extracted from a multiplexed signal. In the pulse detection circuit that is triggered by a trigger signal to generate a detection signal corresponding to the pulse determined by majority decision, a second D-type flip-flop receives a multiplexed signal to the D input and the clear input. and triggering the plurality of first D flip-flops with an output signal obtained by triggering the second flip-flop with a sampling clock pulse that rises within the pulse width of the pulse of the constant period.
It is characterized by triggering type flip-flop. Examples will be described below. FIG. 3 is a circuit diagram showing the configuration of an embodiment of the pulse detection circuit of the present invention, and the same parts as in FIG. 1 are designated by the same numbers.

11 is a D type flip-flop (D-F-F), 12
is its output terminal.

Further, FIG. 4 is a time chart showing signals of various parts in the pulse detection circuit of FIG. 3.

In the figure, a is the input PCM signal, b is the sampling clock pulse, c is the reset pulse, and d is DF-Fl.
1 is the output signal, e is the output signal of D-F-F2, and f is the destuffing signal. In FIG. 3, the multiplexed PCM signal input to terminal 5 is the same as in FIG. 1 (FIG. 4a).

The rising edge of the sampling clock pulse input to terminal 6 must be within the pulse width of the stuff pulse in the multiplexed PCM signal, but the pulse width is different from that shown in Figure 1. , it is not necessary that the pulse width be narrower than the 1-bit pulse width of the stuff pulse, and any pulse width may be used as long as it ends before the arrival of the next stuff pulse (FIG. 4b). D-F-Fll receives such a sampling clock pulse at the clock terminal CLK, reads the logic state of the D terminal at the rising edge of the sampling clock pulse, and is reset at the falling edge of the reset pulse.
Since F-Fll has the D terminal and clear terminal CLE connected, the multiplexed P of terminal 5 connected to the D terminal
When the CM signal is at the "01 level," the D at terminal 12 is
The output signal of -F-Fll becomes a clear ("O") state.

Therefore, the output signal of D-F-Fll is multiplexed PCM
Output with different pulse widths depending on the logic state of the signal (
Figure 4d). The output signal of D-F-Fll is D-F-F2
and is connected to the clock terminal CLK of DF-F3,
As a result, D-F-F2 reads the level equivalent to "1" from battery 1 and outputs "F" to terminal 9 for each output signal pulse of D-F-Fll (Fig. 4e), -F-F3 reads the output state of D-F-F2 at terminal 9 and
-Fll outputs "1" as a destuff output signal to the terminal 10 for each pulse of the output signal (FIG. 4f).

The set pulse (Figure 4c) applied to terminal 7 is D-
It is added to the clear terminal CLE of F-F2 and D-F-F3 to reset D-F-F2 and D-F-F3 at the end of every frame. In this way, D-F-F2 and D-F-
A majority vote of the stuff pulses detected by F3 is performed to generate a destuff output signal. As described above, according to the pulse detection circuit of the present invention, the rising time of the sampling clock pulse only needs to be within the pulse width of the stuff pulse in the multiplexed PCM signal, and the pulse width is different from that in the conventional pulse detection circuit. Since it is not necessary that the pulse width be narrower than the 1-bit pulse width of the multiplexed PCM signal, there is an advantage that the degree of freedom in circuit configuration is increased.

Furthermore, according to the pulse detection circuit of the present invention, when the number of multiplexed clocks increases, the sampling clock pulse is inverted and used to detect the stuff pulses of other channels depending on the rising edge of the sampling clock pulse. Therefore, it is possible to detect the stuff pulses of two multiplexed PCM signals with one series of sampling clock pulses.

As described above, the pulse detection circuit of the present invention is advantageous because the circuit and wiring scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional pulse detection circuit, FIG. 2 is a time chart showing various signals in the pulse detection circuit of FIG. 1, and FIG. 3 is a circuit diagram showing the configuration of the pulse detection circuit of the present invention. FIG. 4 is a time chart showing various signals in the pulse detection circuit of FIG. 3. 1... Battery, 2, 3... D type flip-flop (D-F-F), 4... AND gate, 5... PCM Signal input terminal, 6...
...Sampling clock pulse input terminal, 7...
...Reset pulse input terminal, 8...Output terminal of AND gate 4, 9...Output terminal of D-F-F2, 10...Destaf output terminal, 11.・
...D type flip-flop (D-F-F), 12
・・・・・・Output terminal of D-F-Fll.

Claims (1)

[Claims] 1 comprising a plurality of first D-type flip-flops connected in cascade, triggering with a trigger signal corresponding to a constant period pulse extracted from a multiplexed signal, and detecting the pulse determined by majority vote; The pulse detection circuit that generates the signal includes a second D-type flip-flop to which the multiplexed signal is input to the D input and the clear input, and the second flip-flop is operated within the pulse width of the pulse of the constant period. A pulse detection circuit characterized in that the plurality of first D-type flip-flops are triggered by an output signal obtained by triggering with a sampling clock pulse rising at .