JPH0612893B2 - Time division multiplex transmission system - Google Patents

Description

The present invention relates to a time division multiplex transmission system for time division multiplexing a plurality of digital or analog information signals having different sampling frequencies or clock signal frequencies.

(Background of the Invention) One of the applicants, when receiving a television radio wave from, for example, a broadcasting satellite and retransmitting the received signal to a wired system such as a co-viewing facility, transmits an encoded audio signal. Without demodulating, the signals of a plurality of channels (the channels here mean the number of satellite broadcasting channels corresponding to the number of video channels) in the form of the encoded signals are time-division-multiplexed so that the co-viewing equipment can receive the signals. A patent application has been filed for a time division multiplex transmission method suitable for retransmitting to a transmission path for one channel (Japanese Patent Application No. 254220/1984).
61-133736]).

In this time division multiplexing transmission method, when N channel information signals having different sampling frequencies or clock signal frequencies are time division multiplexed and transmitted through one transmission line, the sampling frequency or clock signal of the N channel information signals is used. A reference clock signal obtained by multiplying the highest frequency or higher frequencies by N,
The N-channel information signal is time-division multiplexed, and a dummy signal is inserted in a portion where the information signal is insufficient to obtain a continuous time-division multiplexed signal.

In this case, it is necessary to send the dummy flag bit in pairs with the dummy signal in order to identify that the dummy signal has been inserted.

As an example of this, in the case where QPSK demodulation is performed on the sound subcarriers of 4 channels of satellite broadcast waves, and the obtained 1-frame 2048-bit (16 bits are frame synchronization bits) bit-streams are multiplexed on 4 channels by the above method. The frame structure in FIG. 3 is as shown in FIG. Third
FIG. 3A shows one frame structure before multiplexing, and FIG. 3B shows an example of the frame structure after multiplexing. In FIG. 3 (b), the dummy flag bit is formed of 8 bits and includes a bit for indicating whether or not the signal of the channel to be transmitted next is dummy data.

However, in the case of the above-mentioned frame structure, when an error occurs in the dummy flag bit in the transmission line (including the transmitting / receiving device), the error cannot be corrected at the time of decoding for separating the original information signal of the multiplexed signal on the receiving side. In addition, there was a problem that the code rate is low (the number of bits is too small).

(Object of the Invention) The present invention has been conceived in view of the above, and an object of the present invention is to provide a time division multiplex transmission system capable of performing error correction when a code error is detected after reception and increasing the code rate.

(Structure and Action of the Invention) In the present invention, when multiplexing N-channel information signals, one dummy flag bit for identifying whether the information signal is a dummy signal is provided for each channel. The flag bits are collected as one block, and an error correction code having a bit number that does not exceed the number of surplus bits generated at the time of multiplexing with one block of dummy flag bits is added to one block of dummy flag bits and transmitted. It is what

Since the dummy flag bit is 1 bit for each channel, the code rate is increased and the number of extra bits is increased.
Other information signals can be transmitted using the surplus bit, and by adding an error correction code, it is possible to detect and correct errors on the receiving side and avoid malfunctions. .

(Examples of the Invention) Hereinafter, the present invention will be described with reference to Examples.

FIG. 1 is a block diagram showing a configuration of a multiplexing unit (encoder unit) according to an embodiment to which the system of the present invention is applied.
The case where information signals of four channels up to are multiplexed is illustrated.

A, B, C, and D are multiplex blocks having the same configuration, and only the common portions with the A channel multiplex block A are shown in detail. The A channel multiplex block A will be described and, if necessary, The other channel multiplexing blocks B, C and D will be described.

A channel code modulation (P
CM) signal A bit stream (hereinafter also referred to as data) having a structure of 2048 bits / frame (including 16 bits of frame synchronization) is supplied to the clock reproduction circuit 2A to reproduce the clock signal A _CK of the A channel. Similarly, input terminal 1B,
Clock signals B _CK , C _CK and D _CK of B, C and D channels are reproduced from B, C and D channel data respectively supplied to 1C and 1D. The regenerated clock signals A _CK , B _CK , C _CK and D _CK are supplied with the highest frequency clock to the highest frequency clock signal selection circuit 3 to select the highest frequency clock signal among them. The clock signal selected by the highest frequency clock signal selection circuit 3 is supplied to the quadrupling circuit 4 to be multiplied by 4 before being supplied to the multiplexed base timing generating circuit 5. The multiplex base timing generation circuit 5 generates read clock signals AR _CK , BR _CK and CR _CK having a frequency four times as high as the maximum clock frequency in each input channel, and various timings required for multiplex (encode). Signal, for example, frame memory MF ₁ to
MF ₄ changeover switch 10A changeover signal, write address counter 7A control signal, read address counter 12A control signal, multiplexers 13A, 16 and 19
To generate a selection signal or the like.

The A channel data supplied to the input terminal 1A is supplied to the frame synchronization detection circuit 6A to detect frame synchronization. The write address counter 7A counts the clock signal reproduced by the clock reproducing circuit 2A, and the write address of the memory block 8A is designated by the count value of the address counter 7A. The information data of channel A is a memory block 8A that constitutes a frame buffer memory.
Is supplied via the changeover switch 10A. In this embodiment the memory block 8A are constituted by 4 frame memory _MF 1 _{~MF 4.} Furthermore, each frame memory is 2032
It is set to bit. During the period when the frame synchronization exists, the write address counter 7A stops counting and the changeover switch 10A is controlled so as to be connected to a non-connected contact, and the changeover switch 10A causes the frame memory MF ₁ , ... MF _{4 for} every 2032 bits of information data. , MF ₁ , ... As a result, information data excluding frame synchronization is stored in the memory block 8A in the frame memory MF.
₁ ... MF ₄ , ... Is stored for each frame.

On the other hand, the read address counter 12A counts the read clock signal AR _CK output from the multiplexed base timing generating circuit 5, and the read address of the memory block 8A is designated by the counted value.

In addition, 2032 bits of data are read from the multiplexed base timing generation circuit 5 for A, B, C, D channels ...
Read clock signals AR _CK and B
R _CK , CR _CK and DR _CK are output in this order. Further, before outputting the read clock signal AR _CK , reading from the memory block 8A is prohibited and a count of the read address counter 12A is stopped for a predetermined bit period. In this embodiment, the predetermined bit set in advance is
It is set to 64 bits.

Therefore, the reading of the information data from the memory block 8A (8B, 8C, 8D) is performed after the 64-bit period after the frame memory MF _h of the memory block 8A, the frame memory MF _k of the memory block 8B, ...
The frame memory MF _{p of} D, the frame memory MF _{(h + 1) of} the memory block 8A after the 64-bit period, ..., The frame memory MF _{(p + 1) of} the memory block 8D, ... Become. On the other hand, the read clock signal has a frequency at least four times as high as that of the write clock signal, but data is read from the memory blocks 8A (8B, 8C, 8D) of the same channel for every four channels. Therefore, an offset is given by default between the write frame memory and the read frame memory, but reading is performed at a faster cycle by the difference between the frequency of the read clock signal frequency and the write clock signal frequency. Due to the difference, the read address is advanced faster.

On the other hand, the count value of the write address counter 7A and the count value of the read address counter 12A are compared by the read relative address discrimination circuit 14A. For example, when data is read from the frame memory MF ₁ of the memory block 8A, When the writing to the frame memory MF ₁ is not yet completed, that is, when there is a shortage of information data, the read / write relative address discrimination circuit 14A stops the counting of the read address counter 12A and the data of one frame is read. Stop reading,
During this time, the multiplexer 13A selects and outputs the dummy data from the ROM 9A in which the dummy data is stored in advance and is always read by the read clock signal AR _CK . As a result, in the multiplexed data, one frame of dummy data is interposed between information data in units of frames, and the data is continuous. Further, the period for inserting the dummy data is a period according to the difference between the frequency of 1/4 of the read clock frequency and the write clock frequency as described above.

As described above, the multiplexer 13A (13B, 13C, 13
The data AD (BD, CD, DD) output from D) is selected by the multiplexer 16 and output.

On the other hand, the read / write relative address discriminating circuit 14A reads data from the frame memories MF _{1 to} MF ₄ when there is insufficient information data and dummy data is inserted as described above, and when there is no insufficient information data as described above. A 1-bit dummy flag bit AF is output in order to make it possible for the receiving side to distinguish between the case where the dummy flag bit AF is performed. Similarly, the multiplexed blocks B, C and D also output 1-bit dummy flag bits BF, CF and DF. The dummy flag bits AF, BF, CF and DF are supplied to the error correction code addition circuit 15 to add an error correction code. In this embodiment, the BCH in the error correction code adding circuit 15
The 3-bit redundant bits generated by the (7, 4) code are added and output.

Therefore, 16 bits forming the synchronization pattern from the synchronization pattern generation circuit 17, 7 bits from the error correction code addition circuit 15, and the remainder bits from the remainder bit generation circuit 18,
41 bits and information data (2032 bits × 4) of A, B, C and D channels from the multiplexer 16 are selected as a block by the multiplexer 19 in this order and output as multiplexed data MD of one frame. Therefore, one frame structure in this case is shown in Fig. 2 (b).
As shown in.

FIG. 2 (a) shows one frame structure before multiplexing, and FIG.
It is the same as (a), and FIG. 2 (c) shows the bit configuration of the dummy flag in FIG. 2 (b).

As described above, one bit is sufficient for each of the dummy flag bits AF, ..., DF, and the error correction code is added. Therefore, if an error occurs in the dummy flag bits on the transmission path (including the transmitter / receiver), reception is performed. On the side, a code error can be detected and corrected at the time of decoding when the original information signal is separated from the multiplexed signal. Further, if the error correction code is added to the dummy flag bits to make 7 bits, the remaining bits become 41 bits and the code rate increases.

(Effect of the Invention) As described above, according to the present invention, dummy flag bits corresponding to each of a plurality of channels are grouped into one block and an error correction code is added, so that when an error is detected on the receiving side. Since error correction can be performed, malfunction can be avoided.

In addition, the dummy flag bit may be one bit for each channel, and therefore the number of extra bits can be large. Therefore, the extra bits are used to transmit the error correction code within the extra bit number in addition to the dummy flag bit. In addition, there is an effect that other information can be transmitted if there are extra bits. Furthermore, since the number of bits obtained by adding the dummy flag bit of one block and the error correction code does not exceed the number of surplus bits, there is an effect that the transmission capacity is not increased.

Furthermore, the number of bits of the error correction code in the present invention required to perform the same degree of error detection and error correction is not proportional to the number of channels, and a dummy flag bit with an error correction code is individually provided at the beginning of each channel. Compared with the case of arranging, the dummy flag bits of 1 bit for each channel are gathered as one block for N channels, and this is generated at the time of multiplexing with the number of dummy flag bits of 1 block. When performing error correction by adding error correction codes of which the number of bits does not exceed the number of surplus bits, it is said that a small number of bits is required for the error correction code required for the same level of error detection and error correction. effective. In addition, this effect becomes more remarkable as the number of channels increases.

Furthermore, if there is a remaining residual bit between the dummy flag bit of one block to which the error correcting code is added and the N-channel information signal, the remaining residual bit is added with the error correcting code. By arranging the block next to the dummy flag bit, there is also an effect that the error correction decoding operation processing time on the receiving side has a margin.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing a frame structure according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing an example of a frame configuration proposed by one of the applicants. A, B, C and D ... A channel, B channel,
C channel and D channel multiplexing block, 2A
...... Clock regeneration circuit, 3 ...... Highest frequency clock signal selection circuit, 4 ...... 4 multiplication circuit, 5 ...... Multiplexing base timing generation circuit, 6 A ...... Frame synchronization detection circuit, 7 A ...
… Write address counter, 8A …… Memory block, 9
A: ROM, 10A: changeover switch, 12A: read address counter, 13A, 16 and 19: multiplexer, 14A: read / write relative address discrimination circuit,
15: error correction code addition circuit, 17: synchronization pattern generation circuit, 18: surplus bit generation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Fujisawa 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology research institute of Japan Broadcasting Corporation (72) Inventor Hiroshi Miyazawa 1-10-11 Kinuta, Setagaya-ku, Tokyo Issue within Japan Broadcasting Corporation Broadcasting Technology Laboratory (56) References Japanese Patent Laid-Open No. 56-141640 (JP, A)

Claims (2)

[Claims] 1. When sampling N (N ≧ 2) channel information signals having different sampling frequencies or clock signal frequencies and time-division-multiplexing them and transmitting them by one transmission path, the sampling frequency of the N channel information signals or A reference clock signal obtained by multiplying the highest frequency of the clock signal frequencies or higher by N
In the time division multiplex transmission system in which the time information division of the channel information signal is performed and a dummy signal is inserted in the portion where the information signal is insufficient to obtain a continuous time division multiplexed signal, each time division multiplexed constituent signal 1 bit is provided for each channel to identify whether is an information signal or a dummy signal, and the dummy flag bits for N channels are grouped as one block.
A time-division multiplex transmission method characterized in that an error correction code having a number of bits which does not exceed the number of surplus bits generated at the time of multiplexing with the number of dummy flag bits of a block is added to one block of dummy flag bits for transmission. 2. The time according to claim 1, wherein the remaining remainder bits are arranged between one block of dummy flag bits added with the error correction code and the N-channel information signal. Division multiplexing transmission system.