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JPS5917580B2 - Television signal noise suppression device - Google Patents
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JPS5917580B2 - Television signal noise suppression device - Google Patents

Television signal noise suppression device

Info

Publication number
JPS5917580B2
JPS5917580B2 JP55081438A JP8143880A JPS5917580B2 JP S5917580 B2 JPS5917580 B2 JP S5917580B2 JP 55081438 A JP55081438 A JP 55081438A JP 8143880 A JP8143880 A JP 8143880A JP S5917580 B2 JPS5917580 B2 JP S5917580B2
Authority
JP
Japan
Prior art keywords
signal
television signal
noise suppression
output
suppression device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55081438A
Other languages
Japanese (ja)
Other versions
JPS5635580A (en
Inventor
敬彦 吹抜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55081438A priority Critical patent/JPS5917580B2/en
Publication of JPS5635580A publication Critical patent/JPS5635580A/en
Publication of JPS5917580B2 publication Critical patent/JPS5917580B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Description

【発明の詳細な説明】 本発明はテレビジョン信号の雑音抑圧装置に係る。[Detailed description of the invention] The present invention relates to a television signal noise suppression device.

テレビの再生画像において、画像が動いている5 場合
、雑音に基づく画質の劣化は視覚上あまり問題とならな
いが、画像が動きの少ないあるいは静止画の場合、雑音
に基づく画質の劣化は無視しがたいものとなる。
When playing images on a TV, if the image is moving5, the degradation of image quality due to noise is not a visual problem, but if the image is a still image or has little movement, the degradation of image quality due to noise cannot be ignored. Become something you want.

このような雑音による画質の劣化を防ぐ目的と10して
第1図に示す如き手段が用いられている。
In order to prevent deterioration of image quality due to such noise, a means as shown in FIG. 1 is used.

すなわち、入力端子1から加えられたテレビジョン信号
Aと後述するフレームメモリ2の出力Bとを演算回路5
、6に加え、演算出力(1部に)A+KBを得る。15
この演算回路Tの出力を出力端子3から出力信号とする
と共に、その一部はフレームメモリ2に記憶する。
That is, the television signal A applied from the input terminal 1 and the output B of the frame memory 2, which will be described later, are input to the arithmetic circuit 5.
, 6, and the calculation output (in one part) A+KB. 15
The output of the arithmetic circuit T is outputted from the output terminal 3 as an output signal, and a portion thereof is stored in the frame memory 2.

ここで、には可変係数であり、動き検出回路4において
、上記信号AとBとの差を求め、この絶20対値が大き
いときはテレビジョン信号は動部分に対応するものとみ
なしに=0とし、入力信号Aがそのまま取り出されるよ
うにする。
Here, is a variable coefficient, and in the motion detection circuit 4, the difference between the signals A and B is obtained, and when this absolute value is large, the television signal is considered to correspond to a moving part, and = 0 so that the input signal A is taken out as is.

一方、信号AとBの差が小さいときは、静止部分に対応
するものとみなし、たとえばに■ 0.5とし、すなわ
ち上記式から一(A+B)となり、AとBの平均を出力
信号として取り出す。
On the other hand, when the difference between signals A and B is small, it is assumed that it corresponds to a stationary part, for example, it is set to 0.5, that is, from the above formula, it becomes 1 (A + B), and the average of A and B is taken out as the output signal. .

これにより雑音成分は抑圧されることになる。しかしな
がら、動き検出回路4を、演算回路5、3θ 6と別に
設ける必要があるなど、上記演算回路あるいは変数にの
制御回路の構成が複雑かつ回路技術上の問題がある。
As a result, noise components are suppressed. However, the structure of the arithmetic circuit or variable control circuit is complicated and there are problems in terms of circuit technology, such as the need to provide the motion detection circuit 4 separately from the arithmetic circuit 5 and 3θ 6.

したがつて本発明の目的は、上述の如きテレビジョン信
号の雑音抑圧装置において簡単な回路構35成によつて
、テレビジョン信号の静止部分におけるランダム性雑音
を抑圧し、高品質のテレビジョン画像を得る装置を実現
することである。
Therefore, an object of the present invention is to suppress random noise in the stationary portion of a television signal by using a simple circuit configuration 35 in a television signal noise suppression device as described above, and to produce a high quality television image. The objective is to realize a device that obtains the following.

本発明は上記目的を達成するため入カテレピジヨン信号
Aと1フレール前のテレビジヨン信号Bの差信号(A−
B)を得て、この差信号の絶対値A−BIの小なる範囲
で、その差信号に対応して差信号に絶対値が1より小な
る可変係数−Kを乗じた値−K(A−B)を固定的な値
を記録したメモリから読み出し、これを上記入カテレビ
ジヨン信号に加えて、雑音を抑圧した出力テレビジヨン
信号A−K(A−B)すなわち(1−K)A+KBとし
て取り出すように構成したものである。
In order to achieve the above object, the present invention provides a difference signal (A-
B), and within a small range of the absolute value A-BI of this difference signal, the value −K(A -B) is read from the memory in which fixed values are recorded, and this is added to the above-mentioned input television signal to extract the noise-suppressed output television signal A-K (A-B), that is, (1-K)A+KB. It is configured as follows.

すなわち、本発明では、所定の演算出力(1一K)A+
KBを得るため差信号をアドレスとしてメモリからのK
(A−B)を読み出す回路を用い、これと入カテレビジ
ヨン信号と加算するという簡単な回路構成によつて、テ
レビジヨン信号において静止部分と動部分で異なる伝達
特性を持たせしめることによつて静止部分に加わるラン
ダム性雑音を抑圧するようにしたものである。以下図面
によつて本発明を詳細に説明する。
That is, in the present invention, the predetermined calculation output (1-K)A+
To obtain KB, use the difference signal as an address to read K from memory.
By using a simple circuit configuration that reads out (A-B) and adding it to the input television signal, the stationary portion and the moving portion of the television signal are given different transfer characteristics. This is designed to suppress random noise added to the image. The present invention will be explained in detail below with reference to the drawings.

第2図は本発明によるテレビジヨン信号の雑音抑圧装置
の一実施例の構成を示すものである。同図において、1
1はテレビジヨン信号入力端子、13は雑音抑圧装置の
出力端子、12はフレームメモリ、14は減算回路、1
5は加算回路、16は固定記憶装置(メモリ)、A,B
,D,Z,Yはいずれも信号を表わす。入力端子11に
加えられたテレビジヨン信号Aはフレームメモリ12の
出力信号Bと共に減算回路14に加えられ、その差信号
D=A−Bを出力する。
FIG. 2 shows the configuration of an embodiment of a television signal noise suppression device according to the present invention. In the same figure, 1
1 is a television signal input terminal, 13 is an output terminal of a noise suppression device, 12 is a frame memory, 14 is a subtraction circuit, 1
5 is an adder circuit, 16 is a fixed storage device (memory), A, B
, D, Z, and Y all represent signals. The television signal A applied to the input terminal 11 is applied together with the output signal B of the frame memory 12 to a subtraction circuit 14, which outputs a difference signal D=A-B.

この差信号Dは固定記憶装置(メモリ)16にアドレス
信号として加えられる。アドレス信号は差信号Dの極性
によつて正番地と負番地が必要であるが、一定値をシフ
トしておいて全ての番地を正番地としても良く、また、
補数表示にすることも可能であることは明らかである。
固定記憶装置16には各番地に種々の値が記録され、差
信号Dの絶対値がある一定数D。より大きい番地にはO
が記録されている。又装置構成上は、Dが大きい所には
メモリを設けなくて、単に出力がOとなる様に構成する
ことができる。差信号Dの値が記憶装置16に与えられ
るとその番地に対応した値が出力zとして得られ、この
出力Zは加算回路15に加えられ、その加算結果A+Z
を出力信号Yとして、出力端子から取り出す。差信号D
が大きいときはZ=0となるので、加算器15の出力は
Y=Aとなる。即ち、動画部分については入力信号Aが
直接出力されることになる。一方差信号Dが零に近い(
DOより小さい)値の場合、即ちテレビジヨンの画像の
静止部分とみなされる部分においては、差信号Dが正す
なわちA>B、のときは記憶装置16から負(Z<O)
の記憶内容が読み出され、加算回路15に加えられる。
This difference signal D is applied to a fixed storage device (memory) 16 as an address signal. The address signal requires positive addresses and negative addresses depending on the polarity of the difference signal D, but it is also possible to shift a certain value so that all addresses are positive addresses, or
It is clear that complementary representation is also possible.
Various values are recorded at each address in the fixed storage device 16, and the absolute value of the difference signal D is a certain number D. O for larger addresses
is recorded. In addition, in terms of the device configuration, it is possible to simply configure the output to be O without providing a memory where D is large. When the value of the difference signal D is given to the storage device 16, the value corresponding to that address is obtained as the output z, and this output Z is added to the adder circuit 15, and the addition result A+Z
is taken out from the output terminal as an output signal Y. Difference signal D
When is large, Z=0, so the output of the adder 15 becomes Y=A. That is, input signal A is directly output for the moving image portion. On the other hand, the difference signal D is close to zero (
If the difference signal D is positive, i.e. A>B, then the negative (Z<O)
The stored contents of are read out and added to the adder circuit 15.

したがつて、出力信号Yの値はAからZの絶対値を減す
るように働くため、即応しない。又差信号が負、すなわ
ちD<Oのときも上述の逆動作とで即応するのを抑える
方向に働く。この結果ランダム性雑音が抑圧されること
になる。なおこのとき Z< D となるように記憶さ
れている。最も簡単な例はIZI−1DI/2である。
土述の実施例によつて説明した如く、本案の装置によれ
ば、単に一般によく知られているメモリ、加減算回路で
構成でき、また、差信号Dと出力zの関係も固定記憶装
置に異つた値を記憶させておくだけで自由に設定できる
。このように特殊の演算回路を必要とせず、実用上極め
て有効な手段を提供するものである。なお、本発明が上
記実施例に限定されるものでないことは明らかであり、
要求される精度コスト、構成上の要求に従つて特許請求
の範囲で、たとえば下記の如く種々の回路構成が可能な
ことは当然である。
Therefore, since the value of the output signal Y acts to reduce the absolute value of Z from A, it does not respond immediately. Also, when the difference signal is negative, that is, D<O, the above-mentioned reverse operation works to suppress the immediate response. As a result, random noise is suppressed. At this time, it is stored so that Z<D. The simplest example is IZI-1DI/2.
As explained in the embodiment described above, the device of the present invention can be constructed simply from a generally well-known memory and an addition/subtraction circuit, and the relationship between the difference signal D and the output z is different from that of a fixed storage device. You can set it freely just by memorizing the value. In this way, the present invention does not require any special arithmetic circuit and provides an extremely effective means in practice. Note that it is clear that the present invention is not limited to the above embodiments,
It goes without saying that various circuit configurations, such as those described below, are possible within the scope of the claims according to the required accuracy cost and configuration requirements.

(1)固定記憶装置16として、いわゆるPLA(プロ
グラマブルロジツクアレイ)を用いる場合。
(1) When a so-called PLA (programmable logic array) is used as the fixed storage device 16.

(2)さらにD。(2) Further D.

を可変にする方法も可能である。たとえば周囲画素が動
画素と判定された場合にはD。を小さく、逆の場合には
大きくするなどである。これは固定記憶装置を複数個用
意し、これを周囲画素の状況で選択してもよい。(3)
装置全体をあらかじめアナログデイジタル変換された信
号により動作される場合、部分的にアナログ信号で動作
させる場合。
It is also possible to make it variable. For example, if the surrounding pixels are determined to be moving pixels, D. In the opposite case, make it smaller, and vice versa. For this purpose, a plurality of fixed storage devices may be prepared and one of them may be selected depending on the situation of surrounding pixels. (3)
When the entire device is operated by signals that have been converted from analog to digital in advance, or when it is partially operated by analog signals.

(4)加算減算について加算器15を減算器として、記
憶装置16の記憶内容を正負反転させる。
(4) Regarding addition and subtraction, the adder 15 is used as a subtracter to invert the stored contents of the storage device 16.

等、本発明の範囲に含まれるものである.又カラーテレ
ビジヨン信号の場合において、フレームメモリの前ある
いは後に色信号成分の反転回路を設けることなど本発明
の装置の中で実施できるものである。
etc., are included within the scope of the present invention. Furthermore, in the case of color television signals, it is possible to implement the apparatus of the present invention by providing a color signal component inversion circuit before or after the frame memory.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の雑音抑圧装置の構成を示す図、第2図は
本発明による雑音抑圧装置の一実施例の構成を示す図で
ある。 11・・・・・・入力端子、12・・・・・・フレーム
メモリ、13・・・・・・出力端子、14・・・・・・
減算回路、15・・・・・・加算回路、16・・・・・
・固定記憶装置。
FIG. 1 is a diagram showing the configuration of a conventional noise suppression device, and FIG. 2 is a diagram showing the configuration of an embodiment of the noise suppression device according to the present invention. 11...Input terminal, 12...Frame memory, 13...Output terminal, 14...
Subtraction circuit, 15... Addition circuit, 16...
- Fixed storage device.

Claims (1)

【特許請求の範囲】 1 入力テレビジョン信号Aとフレームメモリの出力B
の差信号A−Bを得る第1の手段と、上記差信号をアド
レスとしてA−Bに比例する固定的な値を読み出す固定
記憶装置と、上記固定記憶装置の出力と上記入力テレビ
ジョン信号を加算する第2の手段と、上記第2の手段の
出力の1部を上記フレームメモリに入力する第3手段と
を具備してなることを特徴とするテレビジョン信号の雑
音抑圧装置。 2 第1項記載のテレビジョン信号の雑音抑圧装置にお
いて、上記固定記憶装置は上記差信号A−Bをアドレス
信号として加えたとき、上記固定的な値として差信号A
−Bの絶対値|A−B|が特定の値Dより小さい時は−
K(A−B)(Kは絶対値が1より少なる係数)を、か
つ特定の値Dより大きいとき零を読出すように構成され
たことを特徴とするテレビジョン信号の雑音抑圧装置。
[Claims] 1. Input television signal A and frame memory output B
a first means for obtaining a difference signal A-B; a fixed storage device for reading out a fixed value proportional to A-B using the difference signal as an address; A noise suppression device for a television signal, comprising: second means for adding; and third means for inputting a part of the output of the second means to the frame memory. 2. In the television signal noise suppression device according to item 1, when the fixed storage device adds the difference signal A-B as an address signal, the fixed storage device stores the difference signal A as the fixed value.
−When the absolute value of B |A−B| is smaller than a specific value D, −
A noise suppression device for a television signal, characterized in that it is configured to read out K(A-B) (K is a coefficient whose absolute value is less than 1) and read out zero when it is larger than a specific value D.
JP55081438A 1980-06-18 1980-06-18 Television signal noise suppression device Expired JPS5917580B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55081438A JPS5917580B2 (en) 1980-06-18 1980-06-18 Television signal noise suppression device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55081438A JPS5917580B2 (en) 1980-06-18 1980-06-18 Television signal noise suppression device

Publications (2)

Publication Number Publication Date
JPS5635580A JPS5635580A (en) 1981-04-08
JPS5917580B2 true JPS5917580B2 (en) 1984-04-21

Family

ID=13746393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55081438A Expired JPS5917580B2 (en) 1980-06-18 1980-06-18 Television signal noise suppression device

Country Status (1)

Country Link
JP (1) JPS5917580B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166449U (en) * 1985-04-03 1986-10-15

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211885A (en) * 1981-06-22 1982-12-25 Victor Co Of Japan Ltd Noise reduction circuit
JPS5844866A (en) * 1981-09-11 1983-03-15 Hitachi Denshi Ltd solid state television camera equipment
JPS6058777A (en) * 1983-09-09 1985-04-04 Fujitsu Ltd Noise eliminating filter
JPS60111581A (en) * 1983-11-19 1985-06-18 Sony Corp Processor of still picture signal
JPH0681269B2 (en) * 1984-06-30 1994-10-12 松下電器産業株式会社 Video signal processor
JPH0775399B2 (en) * 1986-12-22 1995-08-09 株式会社東芝 Delay calculation circuit and delay calculation method
JPH01123590A (en) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp Video signal processing circuit
JPH02116176U (en) * 1990-02-28 1990-09-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166449U (en) * 1985-04-03 1986-10-15

Also Published As

Publication number Publication date
JPS5635580A (en) 1981-04-08

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