JPH0775399B2 - Delay calculation circuit and delay calculation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a circuit and method for calculating signals before and after delay by a memory.

(Prior Art) As a circuit for calculating signals before and after delay by a conventional memory, there is a noise reduction circuit for reducing noise mixed in a video signal by utilizing frame correlation. This type of noise reduction circuit uses a frame memory as a delay circuit that delays the input video signal by one frame time, and removes noise components from the video signal by utilizing the frame correlation of the video signal. Here, between the video signals separated by one frame,
Generally, the video part has a high correlation and the noise part has no correlation. Also,
When the difference between the two signals separated by one frame is taken, the difference is zero in the video part of the still image part, and the difference value becomes large in the video part of the moving image part, but the noise part remains static. The difference is small regardless of whether it is an image or a moving image. Therefore, it is possible to obtain the frame difference signal and regard the portion where the level of this signal is small as noise. Therefore, the noise reduction circuit reduces noise by extracting a portion having a small level from the frame difference signal and subtracting it from the original video signal.

However, since the conventional noise reduction circuit described above uses the frame memory to obtain a signal delayed by one frame,
There are inconveniences as described below. That is, the frame memory stores an input video signal for one frame, that is, 525 lines, at an arbitrary sampling frequency f _s (for example, horizontal synchronization frequency f _H
M times, where m is an integer), the sampled value sampled as an arbitrary number of quantization steps n bits must be stored, which requires a large-capacity frame memory and increases the cost of the circuit. There was a problem.

(Problems to be Solved by the Invention) In a circuit for calculating a pre-delayed signal and a post-delayed signal by a conventional memory as described above, for example, a noise reduction circuit, one frame, that is, 525 lines of an input video signal is input to a frame memory. However, there is a drawback in that the cost of the circuit is increased because a large capacity frame memory is required. Therefore, the present invention eliminates the above-mentioned drawbacks, and an object of the present invention is to provide a circuit for calculating signals before and after delay by the memory by using a memory having a smaller capacity than the conventional one.

[Structure of the Invention] (Means for Solving the Problems) The delay calculation circuit of the present invention has an input terminal to which a video signal having a video period and a non-video period is input, and a television signal having the video period. A signal discriminating means for discriminating between a riding period and a period during which the non-video period is riding; a memory;
Write control means for writing the video signal in the memory, read control means for reading the video signal written in the memory, video signal written in the memory, and correlation with the video signal A delay time calculation means for calculating a video signal read from the memory, and the video signal is written to the memory when the video period is on the basis of the determination result of the signal determination means. It is characterized in that the video signal is not written in the memory when the non-video period is over.

Further, the delay calculation method of the present invention inputs a video signal having a video period and a non-video period, and discriminates a period in which the video period is superimposed on the television signal and a period in which the non-video period is superimposed. Write the video signal to the memory,
Reading the video signal written in the memory, and calculating a video signal written in the memory and a video signal read from the memory that is correlated with the video signal, According to the signal determination result, when the video period is on, the video signal is written to the memory,
The video signal is not written to the memory when the non-video period is on.

(Operation) In the delay calculating circuit and the delay calculating method of the present invention, only the video period is detected by the signal determining means for determining the period in which the video period is superimposed on the television signal and the period in which the non-video period is superimposed on the television signal. The video signal is stored in the memory, and the video signal is not stored outside the video period.
As a result, the correlation calculation can be performed with a memory having a smaller capacity.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the delay calculation circuit of the present invention. 1 is a subtraction circuit for subtracting a video signal 201 delayed by one frame time from the input video signal 100, 2 is an extraction circuit for extracting a noise component 400 whose level is smaller than the frame difference signal 300 output from the subtraction circuit 1, 3 Is a subtraction circuit for subtracting the noise component 400 from the input video signal 100, and 4 is a noise-free video signal 20 output from the subtraction circuit 3.
A frame memory that stores 0, a switching circuit that selects and outputs either the input video signal 100 or the noise-free video signal 200, and 6 is switching control of the switching circuit 5 and storage control of the frame memory 4. Is a control circuit for performing.

Next, the operation of this embodiment will be described. Input video signal 10
The case where 0 is a luminance signal will be described below. Input video signal 1
00 is input to the subtraction circuit 1, the subtraction circuit 3 and the switching circuit 5. Since the delayed video signal 201 delayed by one frame time read from the frame memory 4 is separately input to the subtraction circuit 1, the input video signal 100 and the delayed video signal 2 are input here.
The subtraction with 01 is performed and the difference is the frame difference signal
300 is output to the extraction circuit 2. This frame difference signal 3
00 is composed of a noise component and a video portion (moving image portion) having no correlation, and the former level has the property of being smaller than the latter level. The extraction circuit 2 is specifically composed of a ROM or the like, separates the noise component and the video component by utilizing the above property, extracts only the noise component 400, and outputs this to the subtraction circuit 3. In the subtraction circuit 3, the noise component 400 is subtracted from the input video signal 100, and the video signal 200 from which the noise component has been removed is output to the terminal b of the switching circuit 5 and the frame memory 4.

Here, within the vertical blanking period of the television signal,
Odd field 10th H (H is horizontal scanning period) to 21st H
There is no video signal between 273H to 284H of the even field (referred to as section A), and further, 14H to 21H of the odd field and 277H to 28 of the even field.
During the period up to 4H (referred to as section B), it is used to insert the test signal of the broadcasting station and the signal for teletext, and in this section B, it is output as it is as an output video signal without noise removal processing. It is desirable to do. Further, since the section A is not displayed on the screen, it is not necessary to perform noise removal processing.

Therefore, the control circuit 6 outputs the control signal 50 to the switching circuit 5 and the frame memory 4 to perform the control as described below. That is, the control circuit 6 receives the input television signal 50.
In the section for n lines (n is an integer) including the section A and the section for n lines including the section B in the vertical blanking removal period of 0, the switching circuit 5 is set to the terminal a side and the input video signal is input.
Controls to output 100 as it is to the next stage. At the same time, the control circuit 6 controls to stop the operation of the frame memory 4 during the section for n lines and stop the storage operation of the video signal 200 output from the second subtraction circuit 3. Also,
When the television signal 500 is present in a section other than the n lines, the control circuit 6 sets the switching circuit 5 to the terminal b side to output the noise-removed video signal 200 and operate the frame memory 4. The video signal 200 is controlled to be stored in this memory. Therefore, the frame memory 4 stores the video signal 200 from which noise has been removed in the section of the television signal 500 excluding the section corresponding to the n lines, and this signal is delayed by one frame time and read out, thereby delaying the delay. The video signal 201 is input to the subtraction circuit 1. In the section of the television signal 500 for the n lines, the input video signal 100 is output from the switching circuit 5 as it is,
The noise-removed video signal 200 is output in a section other than the section corresponding to the n lines. The input video signal 100 is a signal obtained by extracting a luminance signal component from the television signal 500.

According to the present embodiment, in the section where there is no video signal in the television signal 500 and the section where the test signal of the broadcasting station or the character broadcasting signal is inserted, the video signal 20 is stored in the frame memory 4.
Since 0 is not stored, the storage capacity of the frame memory 4 can be reduced and the cost of the circuit can be reduced. Further, in the section where the test signal of the broadcasting station or the teletext signal is inserted, the noise removal processing is not performed and the signal is output as it is. Therefore, the information of the inserted signal is not lost.

Although the above embodiment has described the case where the input video signal 100 is a luminance signal, the same effect can be obtained by applying the present invention even when the input video signal is a color signal.
However, in this case, a chroma inverter circuit for matching the color phase between the frame signals is required after the frame memory. Although the frame memory 4 is used in the above embodiment, a field memory may be used.

[Effects of the Invention] As described above, according to the delay calculation circuit and the delay calculation method of the present invention, it is possible to perform the correlation calculation using a memory having a smaller capacity than the conventional one.

[Brief description of drawings]

FIG. 3 is a block diagram showing a noise reduction circuit which is an embodiment of the delay calculation circuit of the present invention. 1 ... First subtraction circuit, 2 ... Extraction circuit 3 ... Second subtraction circuit, 4 ... Frame memory 5 ... Switching circuit, 6 ... Control circuit

Claims (2)

[Claims] 1. An input terminal to which a video signal having a video period and a non-video period is input, and a period in which the video period is superimposed on a television signal and a period in which the non-video period is superimposed are determined. A signal discriminating means, a memory, a write control means for writing the video signal in the memory, a read control means for reading out the video signal written in the memory, and a video signal written in the memory And a delay time calculation means for calculating a video signal read from the memory and having a correlation with this video signal, and the video when the video period is on the basis of the determination result of the signal determination means. A delay arithmetic circuit, wherein a signal is written in the memory and the video signal is not written in the memory when the non-video period is on. 2. A video signal having a video period and a non-video period is input, and a period in which the video period is carried on a television signal and a period in which the non-video period is carried are discriminated. In the memory, reading the video signal written in the memory, and calculating a video signal written in the memory and a video signal read from the memory that is correlated with the video signal. According to the signal determination result, the video signal is written to the memory when the video period is on, and the video signal is not written to the memory when the non-video period is on. Delay calculation method.