JPS5917883B2 - Polyphase reversible variable frequency oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reversible variable frequency oscillator, and more particularly to a polyphase reversible variable frequency oscillator whose frequency can be changed according to the magnitude of an analog input signal.

Conventionally, there have been few known reversible variable frequency oscillators in which the output signal follows the opposite course after the zero-pass point when the analog input signal changes from positive to negative.
Polyphase reversible variable frequency oscillators are completely unknown.

Therefore, an object of the present invention is to provide a multiphase reversible variable frequency oscillator that can perform frequency control and phase inversion control continuously.

The invention will be explained in more detail below with reference to illustrated embodiments.

FIG. 1 is a diagram showing a single-phase reversible variable frequency oscillator 100.

An analog input voltage ei is applied to an integrator 1 equipped with input polarity switching means.

Switching of input polarity is performed by three resistors 14, 15, 16, an operational amplifier 17, and an electronic switch 18.

Resistors 13 to 15 are selected to have a value R, and resistor 16 is selected to a value R/2.

Therefore, the resistor 14.degree. 15 and the operational amplifier 17 form an amplification circuit with a gain of -1 when the switch 18 is off.

When the switch 18 is on, the gain of this amplifier circuit is 0.
becomes.

Therefore, the voltage value e of the output signal A of the integrator 1.

is expressed as when the switch 18 is off, and is expressed as when the switch 18 is on.

In this way, the polarity of the input voltage ei is switched.

The output signal A of the integrator 1 is sent to two comparators 21 and 22.
The signal is sent to the upper and lower limit detection circuit 2 consisting of the following.

An upper limit value E and a lower limit value -E are separately applied to the comparators 21 and 22 from the upper and lower limit setting circuit 3, respectively.

The output signals of the comparators 21 and 22 are the value e of the output signal A.

When they reach the upper limit +E and the lower limit -E, respectively, they switch to the H level.

The logic circuit 4 includes six NAND elements 41 to 46 and an inverter 47.

The output signal of the polarity determining circuit 5, which is a comparator 51, is at H level when the input voltage is of positive polarity, and is at L level when the input voltage is of negative polarity.

The output signal of the logic circuit 4 controls the on/off of the switch 18.

FIG. 2 shows the operating waveforms of output signals A, B, and C in FIG.

FIGS. 2a and 2b show operating waveforms when the input voltage ei is positive and negative, respectively.

First, as shown in FIG. 2a, when the input voltage ei is of positive polarity and the output signal A is approaching the upper limit value E, the polarity switching means of the integrator 1 is in the inversion operation mode.

That is, the output signal B is at L level and the switch 18 is in the off state.

At this time, in the logic circuit 4, the input terminals above the NAND elements 41 to 44 are each given an L level input signal from the comparator 21 or 22 in the circuit 2.

Further, an H level input signal is applied from the comparator 51 to the lower input terminals of the NAND elements 41 and 43, and an L level input signal is applied to the lower input terminals of the NAND elements 42 and 44 via the inverter 47. It is given.

Therefore, the output signals of these four NAND elements 41 to 44 are all at H level.

The remaining two NAND elements 45 and 46 constitute a flip-flop, and the output signal B of the NAND element 45 is L.
Therefore, the NAND element 46 is at H level.

In other words, the NAND element 45 generates an L level output signal when all input signals are at the H level, and the NAND element 46 generates an H level output signal when only the top input terminal is at the L level. do.

In this state, the output signal A approaches the upper limit value E.

When the output signal A reaches the upper limit value E, the output signal of the comparator 21 in the circuit 2 changes to H level, and therefore the NAN
D element 41.

The input signal applied to the upper input terminal of 44 also changes to H level.

As a result, the output signal of the NAND element 41 changes to L level since all of its input signals become H level.

Since the signal at the lower input terminal remains at the L level, the NAND element 44 maintains the output signal at the H level.

Output signal B of NAND element 45 changes to H level as the input signal led from NAND element 41 changes to L level.

Along with this, the output signal of the NAND element 46 changes to L level.

In this way, the logic circuit output signal B changes to H level at the same time as the integrator output signal A reaches the upper limit value E.

As a result, the switch 18 in the integrator 1 is switched on and the polarity switching means in the integrator 1 is therefore in a non-inverting mode of operation.

Along with this, the integrator output signal A reverses its direction and begins to move toward the lower limit value -E, the output signal of the comparator 21 returns to the L level again, and the input signal of the NAND elements 41 and 44 also returns to the L level.

As a result, only the output signal of the NAND element 41 changes to the L level, but since the lowest input signal of the NAND element 45 is already at the L level, no change occurs in the output signal B.

The output signal A then approaches the lower limit value -E with a slope according to the magnitude of the input voltage ei, and when it reaches the lower limit value -EK, the output signal of the comparator 22 changes to the H level, and N
Only AND element 43 changes its output state.

Therefore, NAND element 46 receives an L level input signal from NAND element 43 and generates an H level output signal.

As a result, all of the input signals of the NAND element 45 go high.
Therefore, the output signal B of the NAND element 45 changes to an L level signal.

As a result, the switch 18 is controlled to the OFF state, the polarity switching means in the integrator enters the inversion operation mode, and the integrator output signal A begins to move toward the upper limit value E again, and accordingly, the output of the comparator 22 The signal returns to L level,
The operating state within the logic circuit 4 is the same as initially assumed.

Thereafter, the same operation is repeated, and as shown in FIG. 2a, a triangular waveform output signal A and a rectangular output signal B are obtained.
, C is obtained.

Next, assuming that the operating state in the logic circuit 4 is the same as initially assumed, the input signal ei is as shown in FIG.
Make the polarity negative.

First, the output signal of the comparator 51 changes to L level,
The signals at the lower input terminals of NAND elements 41 and 43 change to L level, and the signals at the lower input terminals of NAND elements 42 and 44 change to H level, but these NA
Since the signals at the input terminals above the ND terminals 41 to 44 are all at the L level, the output signals of the NAND elements 41 to 44 do not change from the previous H level.

Therefore, the output signal B also remains at the L level, the switch 18 remains off, and the polarity switching means in the integrator 1 maintains the inverting operation mode.

Therefore, only the polarity of the input signal ei changes.

By switching the polarity of the input signal e, the integrator output signal A, which had been heading towards the upper limit value E, begins to move towards the lower limit value -E.

When the output signal A reaches the lower limit value -E, the comparator 22
generates an output signal of H level, and the output signal of NAND element 42 changes to L level, inverting flip-flops 45 and 46.

That is, output signal B changes to H level.

This turns on the switch 18 and switches the polarity switching means in the integrator to the non-inverting mode of operation.

As a result, the output signal A now begins to move towards the upper limit value 10E, and the output signal of the comparator 22 returns to the L level.

Thereafter, as in the case of e1'>00, the output signal A reciprocates between the upper limit value 10E and the lower limit value -E, and its waveform becomes a triangular wave as shown in FIG.

Further, the output signals B and C become rectangular waves as shown on the right side of FIG.

As can be seen from the above explanation, the slope of the triangular waveform of the output signal A is proportional to the magnitude of the input signal ei regardless of the polarity of the input signal e1, and therefore the frequency of the output signal A is
It is proportional to the size of t.

The frequencies of the output signals B and C are also proportional to the magnitude of the input signal ei.

The difference between when the polarity of the input signal ei is positive and when it is negative is that when the polarity is positive, the polarity switching means in the integrator 1 performs an inverting operation during the period when the output signal A moves from the lower limit value -E to the upper limit value 10E. In contrast, when the polarity is negative, the polarity switching means in the integrator 1 is in the non-inverting operation mode during the same period as above.

As can be seen from FIG. 2, if we consider output signal B as a reference, when el>O, output signals A and C
is in phase leading by 90 degrees with respect to output signal B, whereas when ei<0, it means that output signals A and C are in phase behind output signal B by 9 degrees.

That is, by switching the input signal ei, the directionality of the output signals A, B, and C is reversed.

FIG. 3 shows the output signal A when the input signal ei is continuously changed from a positive value to a negative value.

It is a figure showing the time course of B and C.

From this figure, the above-mentioned direction reversal can be understood in more detail.

That is, the direction reversal characteristic of the reversible variable frequency oscillator according to the present invention is such that, in this case, the output signal characteristic is as if the time t were moving backwards in the past, starting from the zero-passing point t=to of the input signal e1. .

FIG. 4 is a block diagram showing an embodiment of the polyphase reversible variable frequency oscillator of the present invention.

A waveform synthesis circuit 200 and a waveform shaping circuit 300 are newly connected in sequence to the cross-phase reversible variable frequency oscillator 100 shown in FIG.

The waveform shaping circuit 300 may be of a generally used type and is not the purpose of the present invention, so a description thereof will be omitted.
00 will be explained below.

FIG. 5 is a diagram showing an embodiment of the waveform synthesis circuit 200 of the present invention.

FIG. 6 is a diagram showing the output waveform of the waveform synthesis circuit 200 of FIG. 5.

In this embodiment, three-phase output is obtained.

The output signal A of the oscillator 100 is set as the R phase of a three-phase alternating current, and the R phase is used to synthesize the S phase and T phase waveforms to obtain a three phase triangular waveform.

From the A=R waveform, synthesize the waveforms at points p and Q in FIG. 5, that is, the waveforms shown as P and Q in FIG.
By combining these signals with the analog switches 56 and 57, which can be connected to the digital signal of the output signal B of the oscillator 100, the waveform and T waveform are obtained.

The P waveform in FIG. 5'ΔC is the R waveform modified by operational amplifiers 50 and 51, and is shown by a broken line in FIG.

In the operational amplifier 50, 1:1 inversion is performed as shown in the figure with reference to the voltage level of 10E/3, and the operational amplifier 51
When the signal attempts to exceed the voltage level of 10E by the action of 10E and the diode D, a 1:1 inversion is performed with 10E as a reference.

The resistors R in the figure are for 1:1 inversion, and in principle they can all have the same value.

Similarly to the above, for the Q waveform, the operational amplifiers 52 and 53 perform a 1:1 inversion of the signal based on the voltage level of -E/3.

Since the switching signal B from the oscillator 100 to the analog switches 56 and 57 is switched only at the point where the voltage level of the P waveform minus the voltage level of the Q waveform is established, there is no discontinuity in the S and T outputs, and During normal rotation, R, S, and T are 1 in this order.
It plays an important role of switching so that when the reverse rotation is delayed by 20 degrees, the 8 △ △ R, T, and S are delayed by 120 degrees.

The combined S and T waveforms during this forward rotation are shown at the bottom of FIG.

Operational amplifiers 54 and 55 are buffers for impedance conversion.

In this way, the synthesis of the S and T waveforms, which are delayed by 120 degrees from the R waveform, can be accurately shifted by 120 degrees regardless of the frequency, unlike a delay using a capacitor C or a resistor R.

In order to make it easier to understand the operation of a three-phase reversible variable frequency oscillator, Figure 7 shows an example where the input ei is an angular velocity, and the time t
FIG. 4 is a diagram showing the relationship between the rotation angle ωt (or distance) and the R, S, and T outputs.

As shown in FIG. 7C, the graph of t-ωt in FIG.

There is no discontinuity in the R, S, and T waveforms, and switching between forward and reverse is also performed continuously and smoothly.

FIG. 8 is a diagram showing another embodiment of the polyphase reversible variable frequency oscillator of the present invention.

That is, it is a two-phase reversible variable frequency oscillator 210 that outputs waveforms R and X that are 90 degrees out of phase.

FIG. 9 shows the output waveform of this embodiment.

When the output signal B from the oscillator 100 is at H level and L level by the analog switch 65 in FIG. 8, x=
p'Δ and X=Q', and the waveform X is synthesized and output.

It is well known that once two-phase and three-phase outputs are obtained, signals at any other angle can be obtained.

The effects of the present invention are that if two-phase and three-phase variable frequencies can be obtained with inexpensive equipment, performance in AC variable continuous control can be improved, and it is possible to manufacture ultra-high precision oscillators or fast-response synchronous filters. For example,

[Brief explanation of drawings]

FIG. 1 is a diagram showing a single-phase reversible variable frequency oscillator. FIG. 2 is a diagram showing operating waveforms of each part in FIG. 1. FIG. 3 is a diagram illustrating each output of the oscillator in FIG. 1. FIG. 4 is a block diagram showing a polyphase reversible variable frequency oscillator of the present invention. FIG. 5 is a diagram showing an embodiment of the waveform synthesis circuit of the oscillator of the present invention. FIG. 6 is a diagram showing the output waveform of the embodiment of FIG. 5. FIG. 7 is a diagram illustrating the output waveform of the oscillator of the present invention. FIG. 8 is a diagram showing another embodiment of the waveform synthesis circuit of the oscillator of the present invention. FIG. 9 is a diagram showing the output waveform of the embodiment of FIG. 8. Description of symbols, 1... Integrator, 2... Upper and lower limit detection circuit,
3... Upper and lower limit setting circuit, 4... Logic circuit, 5...
Polarity discrimination circuit, 50, 51, 52, 53... operational amplifier, 54.55... operational amplifier, 56, 57... analog switch, 60, 61, 62, 63... operational amplifier, 64. ...Operation amplifier, 65...Analog switch, 100...Reversible variable frequency oscillator, 200,2
10... Waveform synthesis circuit, 300... Waveform shaping circuit.

Claims (1)

[Claims] 1. A reversible variable frequency oscillator that outputs a variable frequency according to an analog input signal, a waveform synthesis circuit that generates a continuous phase multiphase output of the same frequency as the frequency using the output from the reversible variable frequency oscillator, and A polyphase reversible variable frequency oscillator comprising a waveform shaping circuit that shapes polyphase output from a waveform synthesis circuit into a desired waveform.