JPS59170B2 - variable frequency oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable frequency oscillator whose frequency can be changed depending on the magnitude of an analog input signal.

This type of oscillator is called a voltage/frequency converter when the output signal has a pulse waveform, and various circuit configurations are known.

However, few variable frequency oscillators are known that have reversible characteristics, such that when the analog input signal changes from positive to negative, the output signal follows the opposite course after the analog input signal passes through zero. Not yet.

This type of characteristic can be achieved by a synchronous generator driven by a DC motor or a pulse encoder whose rotational speed and direction are controlled according to the magnitude and polarity of the armature voltage. It can be realized.

That is, in this case, the frequency of the output signal of the synchronous motor or pulse encoder can be changed depending on the magnitude of the armature voltage of the DC motor, and reversible characteristics can be obtained depending on the polarity of the armature voltage. It will be done.

An object of the present invention is to construct a variable frequency oscillator having reversible characteristics as described above by electronic means.

This object is achieved according to the invention by the features described in the claims.

Hereinafter, embodiments of a reversible oscillator according to the present invention will be described without reference to the drawings.

According to the embodiment of the present invention shown in FIG. 1, 1 is an integrator equipped with input polarity switching means, and is guided by an input voltage (analog input signal) ei.

This integrator 1 includes an integrator part having a known configuration including an operational amplifier 11, an integrating capacitor (capacitance C1) 12, and an input resistor 13, as well as three resistors 1 for input polarity switching.
4, 15, 16, operational amplifier 17, and electronic switch 18
It has an additional circuit section consisting of.

Resistors 13-15 are chosen to have equal values R, and resistor 16 is chosen to be half that value R/2.

Therefore, the resistors 14 and 15 and the operational amplifier 17 constitute an amplifier circuit with a gain of -1 (provided that the switch 18 is in the OFF state).

When the switch 18 is on, the feedback resistor 15 is short-circuited, so the gain of this amplifier circuit is zero.

Therefore, the voltage value e of the output signal A of the integrator 1.

can be expressed as when the switch 18 is off, and can be expressed as when the switch 18 is on.

Therefore, the original polarity of the input voltage ei can be switched and transmitted to the integrator by the switch 18.

Other known means may be used as such polarity switching means.

The output signal A of the integrator 1 is guided to the upper and lower limit detection circuit 2.

This circuit 2 is composed of two comparators 21 and 22.

Upper limit values E and -E are respectively led to the comparators 21 and 22 from the upper and lower limit setting circuit 3.

The output signal of the comparator 21 is the value e of the output signal A of the integrator 1.

When reaches the upper limit value E, it switches to H level, and the output signal of the comparator 22 is equal to the value e□ of the output signal A of the integrator 1.
When reaches the lower limit value -E, it switches to H level.

The output signals of both comparators 21 and 22 are led to logic circuit 4.

The logic circuit 4 also receives an output signal from a polarity determining circuit 5 comprising a comparator 51 receiving the input voltage ei.

This logic circuit 4 is composed of six NANI pins 41 to 46 and an inverter 47.

The output signal of the polarity determination circuit 5 becomes H level when the input voltage ei has positive polarity, and becomes L level when the input voltage ei has negative polarity.

The output signal of the logic circuit 4 controls the on/off of the switch 18.

FIG. 2 shows the respective operating waveforms of the output signal A of the input voltage e'lz integrator, the output signal B of the logic circuit 4, and the output signal C of the comparator 6 for determining the polarity of the output signal of the integrator 1. The waveform on the left side is when the input voltage e. is positive polarity, and the waveform on the right side is when the input voltage ei is negative polarity.

First, it is assumed that the input voltage e is of positive polarity as shown on the left side of FIG. 2, and that the integrator output signal A is approaching the upper limit value E.

The polarity switching means within the integrator 1 are therefore in the inversion mode of operation.

That is, the logic circuit output signal B is at L level and the switch 18 is in the off state.

At this time, in the logic circuit 4, the upper input terminal of the Nm children 41 to 44 is connected to the comparator 21 or 22 in the circuit 2.
An input signal of L level is given to each of NAND elements 41 and 43, and an input signal of H level is given to the lower input terminals of NAND elements 41 and 43 from comparator 51 in circuit 5. An L level input signal is applied to the lower input terminal via an inverter 47.

Therefore, the output signals of these four NAND elements 41 to 44 are all at H level.

The remaining two Nm children 45 and 46 constitute a flip-flop, and since the output signal B of the Nm child 45 is at L level, the one child 46 in N has an H level, so the Nm child □
46 is at H level.

In other words, all the input signals of N's 1 child 45 are at H level and generate an L level output signal, and N's 1 child 46 generates an L level output signal.
Only the top input terminal is at L level and generates an H level output signal.

In this state, the output signal A approaches the upper limit value E.

When the output signal A reaches the upper limit value E, the output signal of the comparator 21 in the circuit 2 changes to H level, so that NAn
The input signals applied to the upper input terminals of the children 41 and 44 also change to H level.

As a result, the output signal of the N terminal 41 changes to the L level since all of its input signals become the H level.

Since the signal at the lower input terminal remains at the L level, the NAM element 44 maintains the output signal at the H level.

The output signal B of the AND element 45 is
When the input signal led from the input signal changes to L level, it changes to H level.

Along with this, the output signal of the first child 46 changes to the L level.

As described above, at the same time as the integrator output signal A reaches the upper limit value E, the logic circuit output signal B changes to H level.

The switch 18 in this integrated integrator 1 is switched on, so that the polarity switching means in the integrator 1 are in a non-inverting mode of operation.

Along with this, the integrator output signal A reverses its direction and begins to move toward the lower limit value -E.

Along with this, the output signal of the comparator 21 becomes L again.
The input signal of Nm child 4L 44 is also low.
Return to level.

As a result, only the first child of the NAND* child 41 changes, and this output signal becomes L level.

The change of the output signal of the Nm child 41 to the L level is caused by the change of the output signal of the Nm child 41.
Since the lowest input signal of 5 is already at L level, this N
Unless the lowest input signal of the AND element 45 is already at the L level, no change is caused in the output signal B of the first element 45.

The integrator output signal A then approaches the lower limit value -E with a slope according to the magnitude of the input voltage ei.

As soon as the output signal A reaches the lower limit value -E, comparator 2
The output signal of comparator 2 changes to H level, and the output signal of comparator 2 changes to H level.
Only 43 of the Nm children 42.43 receiving input signals from 2 change their output state.

As a result, NAM child 46 receives the L level input signal from Nm child 43 and emits an output signal changed to H level.

As a result, all of the input signals of the NAND element 45 go high.
Therefore, the output signal B of the NAND element 45 changes to an L level signal.

As a result, the switch 18 is controlled to the OFF state, the polarity switching means in the integrator enters the inversion operation mode, and the integrator output signal A begins to move toward the upper limit value E again, and accordingly, the output signal of the comparator 22 returns to L level.

Since the output signal of the comparator 22 returns to the L level, the operating state in the logic circuit 4 becomes the same state as initially assumed.

Thereafter, the same operation is repeated, and a triangular waveform output signal A and rectangular waveform output signals B and C are obtained as shown in 5 on the left side of the second operation.

Now, assuming that the operating state in the logic circuit 4 is the same as initially assumed, let us try changing the polarity of the input signal ei from positive to negative in a stepwise manner.

As a result, the output signal of the comparator 51 first changes to L level.

As a result, the signals at the lower input terminals of the NAND elements 41 and 43 change to the L level, and the signal at the lower input terminal of the NAND elements 42 and 44 changes to the H level. Since all the signals at the upper input terminals are at L level, the output signals of NAM elements 41 to 44 do not change from the previous H level.

Therefore, the output signal B also remains at the L level, the switch 18 remains off, and the polarity switching means in the integrator 1 maintains the inverting operation mode.

Therefore, only the polarity of the input signal ei changes.

By switching the polarity of the input signal et, the upper limit value E
The integrator output signal A, which was heading towards the lower limit value -E, now changes direction and starts heading towards the lower limit value -E.

As soon as the output signal A reaches the lower limit value -E, the comparator 22 issues an output signal of H level, which causes the output signal of the m terminal 42 to change to the L level and the flip-flop 4
5. Invert 46.

That is, output signal B changes to H level.

This turns on the switch 18 and switches the polarity switching means in the integrator to the non-inverting mode of operation.

This integrated integrator output signal A now begins to move toward the upper limit value -'knee E, and the output signal of the comparator 22 returns to the L level.

Thereafter, as in the case where ei>0, the output signal A reciprocates between the upper limit value E and the lower limit value -E, and its waveform becomes a triangular wave as shown on the right side of FIG.

Further, the output signals B and C become rectangular waves as shown on the right side of FIG.

As can be seen from the above explanation, the slope of the triangular waveform of the output signal A is proportional to the magnitude of the input signal ei regardless of the polarity of the input signal ei, and therefore the frequency of the output signal A is
・Proportional to the size of.

From this, it goes without saying that the frequencies of the output signals B and C are also proportional to the magnitude of the input signal ei.

The difference between when the polarity of the input signal e. In contrast, when the polarity is negative, the polarity switching means in the integrator is in the non-inverting operation mode during the same period as above.

As can be seen from Fig. 2, when considering output signal B as a reference, when e 1 > 00, output signals A and C lead phase by 90 degrees with respect to output signal B. On the other hand, when ei<0, it means that the output signals A and C are delayed in phase by 90' with respect to the output signal B.

That is, by switching the input signal ei, the directionality of the output signals ppB and C is reversed.

FIG. 3 shows an output signal A when the input signal ei is continuously changed from a positive value to a negative value.

The time course of B and C is shown, and the above-mentioned reversal of directionality can be understood in more detail from this figure.

That is, in this case, the direction reversal characteristic of the reversible oscillator according to the present invention becomes an output signal characteristic as if the time t were reversed in the past, starting from the zero-passing time t-to of the input signal ei.

This characteristic is the same as that brought about by the mechanical means mentioned above, and the input signal ei can be likened to the rotational speed, and the integrator output signal A changes direction at E above the upper and lower limits. The movement of the output signal A (see the waveform additionally shown at the bottom of Fig. 3) when it is assumed that the rotation angle does not change can be compared to the rotation angle with respect to the rotation stop point (rotation direction reversal position). can.

As described above, according to the present invention, not only frequency control but also phase reversal control can be performed continuously by input signal ei, and an oscillator having such characteristics can be used, for example, in the field of variable frequency control of alternating current machines. It can be applied as a voltage or current instantaneous value command means.

For example, for a three-phase alternating current machine, the output signal A (but still B) of the reversible oscillator according to the invention.

C) is converted into a three-phase output signal by phase number conversion, and this can be used as an instantaneous value command signal for three-phase voltage or current by performing waveform shaping such as sineization as necessary.

In this case, the magnitude of the input signal ei of the reversible oscillator commands the frequency, and the switching of the polarity of the input signal ei causes the reversal of the phase rotation direction to occur without impact.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are diagrams explaining the operation of the embodiment. 1... Integrator equipped with input polarity switching means, 2...
Upper and lower limit detection circuit, 3... Upper and lower limit setting circuit, 4... Logic circuit, 5... Polarity discriminator.

Claims (1)

[Claims] 1. An integrator to which an analog input signal is guided via a manual polarity switching means, an upper/lower limit detection circuit for detecting that the output signal of this integrator has reached a predetermined upper limit value and lower limit value, and a polarity discriminator for discriminating polarity, receiving an upper limit reaching signal and a lower limit reaching signal of the upper and lower limit detection circuits, and an output signal of the polarity discriminator;
When the upper limit value is reached, the output signal of the integrator is directed toward the lower limit value, and when the lower limit value is reached, the output signal of the integrator is directed toward the upper limit value. A variable frequency oscillator comprising: a logic circuit that controls the input polarity switching means according to the determined operation mode until receiving and receiving an upper limit reaching signal or a lower limit reaching signal from a lower limit detection circuit.