JPS59178B2 - digital phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the digitization of phase-locked loops, such as phase-locked loops and Costas loops.

With the development of digital technology in recent years, circuits that were conventionally constructed using analog circuits have been digitized, and some have been implemented as LSIs.

In recent years, research has been underway to convert phase-locked loops, which are used to generate carrier oil from amplitude-modulated waves and demodulate frequency-modulated waves, into digital signals.

FIG. 1 shows the configuration of a digital 7A lock loop.

Input 10 is the sampled sequence x(n).

The output 19 is a series y(n) obtained by sampling a sine wave.

The multiplication circuit 11 serves as a phase comparator, and the sampling interval T is x(n)=sin (WCn T+θ) y(n)=house(WCn T ).

The digital low pass filter 13 reduces the double frequency component of the carrier in the above equation and determines the characteristics of the loop.

This filter is for example It can be something as simple as .

(At this time, many 2 WC components are mixed in 14) Let the output of the filter be w0.

An adder 15, a phase designation memory 16, and a sine wave generator 18 constitute a digital vCO.

The sine wave generator 18 outputs the amplitude value of the sine wave corresponding to the phase 17 designated by the phase designation memory 16.

For example, assume that 36,000 phases are divided into 32 equal parts.

If the phase designation memory specifies "15", the output of 18 is set to output the value 2 of cos (360'X-).

170 phase phase designation circuit (n) = v (n-1) + C+
w(n-1).

C specifies the center frequency of vCO, w(nl) is vCO
becomes the control signal.

For example, if the control signal is always O, the phase designation is C at every time T.
The center frequency F.

Hato becomes.

When the vCO control voltage w(n) is positive, the phase advances quickly, which corresponds to increasing the oscillation frequency of vCO.

The opposite is true when W(to) is negative. Therefore, in equation (1), if θ>0, the low pass filter 13 will reduce the DC component by -5 inches.
Since θ is emphasized, the vCO control signal becomes positive, and vC
The output of O is controlled in the phase advance direction.

If θ〈O, the opposite is true. A Costas loop is a loop that extracts a carrier component from a DSB waveform.

A block diagram of the Costas loop is shown in FIG.

Input 20 is converted into DSB waveform A(t)cos (WCt+θ
).

If the output 30 of the VCO 29 is sin (wot), eA(t) of the output 22A of the phase comparator 21A is eA(t
)=A(t)cos (WCt+θ)8 koku(w(2t
) VCO output 30 passes through a 90° phase shifter 31 and outputs 32
-cos (′”Ct) is obtained as .

eB (t) of Tagata 22B of phase comparator 21B is LPE 23A and 23B twice the frequency of the carrier, □ Equation 2
This is to cut the modulation component caused by wo, and hA(t) and hB(t) of the outputs 24A and 25B are the output g(t) of the multiplication circuit 25. Therefore, the LPF 27 is If it passes through, a value proportional to 5 in 2θ can be obtained as the VCO control signal 28, so the output of the vCO can be locked with the input.

The Costas loop has a 180° ambiguity in locking phase.

, this Costas loop is also phase-locked in Figure 1.
7. It goes without saying that it can be digitized like a loop. C.

Although a sine wave generating circuit is used in the above loop, it goes without saying that the phase-locked loop also works with a repetitive wave such as a triangular wave instead of a sine wave.

The low pass filter in Figure 1 13 has the function of determining the loop characteristics and the function of reducing the frequency component twice the input (synchronous frequency), but the filter that reduces the double frequency component and the function of determining the loop characteristics You can also consider dividing it into filters.

In particular, if you want to make the loop characteristics variable, the filter that reduces the double frequency component should have a pass band as flat as possible in the low frequency part, and the attenuation around the double frequency should be thick.

The filter that determines the loop characteristics has a simple structure, and changes the loop characteristics by changing the low-frequency characteristics.

This will be called a loop filter.

This filter does not need to have a large attenuation around the double frequency.

The difference in characteristics between the two filters is, for example, as shown in FIG.

In the Costas loop, the filters for double frequency removal are 23A and 23B1 loop filter 27 in FIG.

For example, a loop filter having the following transfer characteristics is used.

The configuration of a filter having the characteristics described above is shown in FIG.

Reference numerals 42 in FIG. 4a and 57 in FIG. 4b are memories for delaying one sampling period.

44 and 54 are circuits that multiply the input by a times.

46 and 51 are circuits that multiply the input by b times.

The transfer function from 41 to 48 is 1-b21.56 to 53
The number of transmission surfaces 1-b2” is □.

Since F(z) is a low pass filter, 1 and a>b, so a-b(1), so in order to obtain the same output value, the 56 signal is 41 The configuration shown in FIG. 4b has less possibility of memory overflow.

Therefore, the following mainly describes the configuration shown in FIG. 4.

The signal 53 corresponds to FIG. 14 as a control signal for vCO.

The control signal takes a non-zero value when the input frequency deviates from the center frequency of vCO (determined by constant C).

Furthermore, in the transient state of synchronous pull-in, if the damping factor of the loop is small, the control signal will take an oscillatory value.

Therefore, the control signal must have a certain range of variation.

For example, if the phase of the sine wave generation circuit changes by 360°/128 with respect to the magnitude of the control signal "1", and if the sampling frequency is 16KHz, the magnitude of the control signal "1" will be 16KHz/128 = 125Hz
This means that the oscillation frequency of the VCO is shifted from the center frequency by this amount.

Since the center frequency is determined by the constant C, for example, C=2
If it is 0, the center frequency is 125Hz x 20 = 2500
It becomes Hz.

Here, assuming that the control signal can be changed in the range of +1 to -1, the limit of the hold range (the range in which phase synchronization can be maintained even if the input frequency is shifted) determined from the bird's loop characteristics is 2500 Hz. ±125Hz.

Generally, the hold range determined by the loop characteristics of a phase-locked loop is much wider than this, but if the input frequency range is limited, it is okay to set a limit on the hold range on the birdware.

However, it is not preferable to reduce the hold range determined by the loop characteristics because this increases the residual phase error.

If the input frequency range is determined in this way, the hold range on the bird can be made much narrower than the theoretical hold range.

In addition to the hold range, another important characteristic is the lock-in range (frequency range in which periodic pull-in occurs).

A lock-in range requires synchronization when an input frequency within that range comes in, and the lock-in range is much narrower than the hold range.

If the theoretical lock-in range is wider than the hold range limit determined from the first half bird, the lock-in range will also be limited by the bird.

Therefore, we want all frequencies within this bard limit to be locked in.

However, if an input frequency that is actually close to the limit point comes in, and if the transfer function system from the loop input phase to the VCO output phase is under dumped, it will take until it reaches the final value as shown in Figure 5. There is overshoot, and the limit point may be exceeded during transient conditions.

It is sufficient to choose a constant so that the transient characteristics do not have overshoot, but if the damping factor of the system is made too large, the convergence time until a stable state is reached will be long (decreased).

Furthermore, since the characteristics of the system change depending on the input amplitude, etc., it is difficult to always ensure that the convergence time is fast in a transient state and there is no overshoot.

Therefore, it is desirable to have a design that allows for overshoot.

The present invention achieves this objective. In FIG. 4, the transfer function of Ibz' from the signal 56 to the signal 53 is □, and the overflow of 530 -b and the overflow of 56 do not have a one-to-one correspondence.

Since 53 is added to a large number (constant O) after this, if an MSB hold circuit is provided at 50 and 58 to expand the MSB (sign bit), the overflow at 53 can be avoided.
Flow is a problem.

The circuit configuration in this case is as shown in FIG.

61 and 66 are the above MSB hold circuits, and the signal is L.
This circuit holds the polarity of MSB for a certain period of time when it is input in series from SB.

For example, assume that the signal at input 60 is represented by 5 bits including the sign bit.

The display range is a number less than 1 and greater than or equal to -1.

It is also assumed that the memory 64 has a capacity of V:, 5 bits.

Let's make the signals 60 and 65 as follows.

However, negative numbers are expressed in two's complement.

[60] 1o base = -0,375 [60) binary = 1.10
10 [65) decimal = -0, 75C65, + binary = 1.
0100 The above binary representation is assumed to be displayed starting from the MSB, with the MSB being a sign bit and a decimal point following the MSB.

If there is no MSB hold (same as the circuit in Figure 4), the output 68 will be [68] binary = 10.1110 and will overflow.

Therefore, if you have an output of 68 and hold the polarity at the MSE position (to the left of the decimal point) of 68 in order to add it to a large number (constant C), [68] binary MSB hold = 0000.1110 and C = 10 (2 When added to 1010.) in decimal, it becomes 1010.1110 (10.875 in decimal),
It cannot be expressed in binary as 10-0.75-0.375 = 8.875.

As shown in FIG. 6, if an MSB hold circuit is provided and further 3-bit expansion is performed, (62, + binary = 1111.1010 [67] binary = 1111.0100, [68,] binary = 1110.1110 This becomes 1010. If added, it becomes 0100.1110, which is 8.875 in decimal notation, so there is no need to worry about overflow in signal 68.

However, overflow at 63 becomes a problem.

-b The transfer function from 68 to 63 is and 1-b2
' 68 overflow is now 3-63 overflow
Although it is not a flow, when a=1, 68 and 63
There is no big difference in size.

For ease of understanding, the explanation will be based on the case where a = 1. Signal 68 is the addition of signal 62 and signal 67, but when synchronization occurs, signal 62 becomes O, and signal 67 becomes the same as signal 68.

In other words, the signal 63 has the same magnitude.

Now, in a system like this (in the two's complement notation used, the maximum positive value and the maximum negative value are adjacent to each other.

For example, if it is a 5-bit display (MSB is the sign bit),
The maximum positive value (0.9375 in decimal) is 0.1111, and the maximum negative value (-1 in decimal) is expressed in binary as i, oooo.

Therefore, if 0.0001 is added to the maximum positive value, it will overflow and become the maximum negative value.

If the system is under dumped, the vCO output frequency will jump significantly when signal 63 overflows as shown in FIG.

It approaches the input frequency again, but since the overshoot has become large, it has no choice but to overflow again.

In this way, if the system is under dumped and an overflow occurs in the signal 63 during the lock-in transient state, lock-in will no longer be possible.

The present invention eliminates the above disadvantages.

In the above case, even if the signal 63 exceeds a certain limit, it is sufficient to keep it within that limit.

No. 63. I=(C signal 67)+C signal 62])×a-
[Signal 62) Xb = (Signal 57: lXa + [Signal 62)
(a-b) If 1≦a)b and signal 67 is below the limit value and signal 62 is also below, then signal 63 is over 2 bits or more.
There is no flow.

For example, if the size is as follows [69] Binary = 0000.1110 [70] Binary = 1111.1011 [63) Binary = [69] Binary - C70, + Binary = OOO
1,0O11 Also, in the following case C69) Binary = 1111.0O10 [70] Binary = 0000.0101 [63] Binary = 1110.1101 An overflow car has occurred and the lower limit has been exceeded.

Therefore, look at the two digit bits above the decimal point and get tt 01p
If it reaches p, the upper limit is exceeded, and if it reaches "10", the lower limit is exceeded.

Therefore, if the upper limit is exceeded, the upper limit is ``0.1111''.
", and if it exceeds the lower limit, lower limit value" 1.000
0'' and store it in the memory 64.

Further, the signal 65 may be corrected when output from the memory without changing it when stored in the memory 64.

In this way, the control signal 68 is locked into the synchronized state without jumping as shown in FIG. 8, for example.

FIG. 9 shows an example of the circuit configuration of a filter according to an embodiment of the present invention, and FIG. 10 is a time relationship diagram of the operation of each part.

The input signal 80 in FIG. 9 is input as a 5-bit serial signal from the LSB.

The MSB bit (last bit) is the sign bit.

Figure 10a shows the time relationship, where the batch part is the part where the signal is, and the V mark is the position of the decimal point.

Input is made only once during one sample interval.

The MSB hold circuit is a circuit that expands the sign bit for a certain period of time, and usually involves a one-bit delay.

In FIG. 10, the 6 bits after the V mark have the same sign.

asb is a positive number from O to 1, and a total of 5 bits, 4 bits below the decimal point and 1 bit above the decimal point (it becomes 1"1" only when the value is 1), is input in parallel to the multiplication circuits 86 and 83. shall be carried out.

The result of multiplication is as shown in Figure 10C, where the decimal point is LS.
It is between the 8th and 9th bits from B.

At this time, the sign bit is the bit next to the decimal point.

The rounding circuit 91 is a circuit that rounds the 4th bit from the LSB of the signal 90 (discards 0 and discards 1), and its Tagata signal is shown in Figure 10 d.
become that way.

It is assumed that memory 09 has a capacity of 5 bits.

If there is no overflow in 92, the P bit and Q bit in FIG. 10d will have the same sign (1" or uO").

If an overflow occurs and the upper limit is exceeded, P=1. Q
=0.

When the lower limit is raised, P=0 and Q=1.

Therefore, the exclusive OR (XOR) of P bit and Q bit
If it becomes 1, it means that there was an overflow.

93 is a circuit for ebit delay, and since the P bit % is at 94 and the Q bit is at 92 at the timing of clock A, XOR is performed at 95 and stored in 98 at the timing of clock A.

Also, 97 has P focus memorized.

Data 97 and 98 are rewritten with new data at the timing of clock A, which occurs once in one sampling period.

Therefore, when there is an overflow, 101 becomes 1''
, and when it exceeds the upper limit, 100
becomes Pa1", and when it exceeds the lower limit, 100 becomes u
It has become Ojj.

What we want to input to the 5-bit memory 09 is the operation result 92 (1-bit shift 93) when there is no overflow.
and is shifted by 6 bits by 5-bit shift 105 to become 106] If the upper limit is overflowed, the value is "11110" from the LSB, and when the lower limit is overflowed, it is "00001" from the LSB.

Therefore, if the fixed pattern 102 (Fig. 10g) and 100 are XORed, 104 will contain "11110" when the upper limit overflows and "11110" when the lower limit overflows. o o
o o i” is displayed.

107 is a λND-OR gate, and 108 outputs the same signal as 104 when there is an over/lower level, and the same signal as 106 when there is not.

Therefore, 109 only needs to memorize 108.

The 10th diagram is a clock diagram when 109 is a shift register, and the X clock group is necessary for output,
X clock groups are required at input.

As described above, when the calculation result 92 overflows the upper limit, the upper and lower limit values of tto, 1111'' from the MSB, and 1.0000 when it overflows the lower limit are stored in 109. vC
O's ram signal 85 no longer jumps significantly, and there is no worry that locking will not occur even if there is an overflow in the lock-in transient state.

[Brief explanation of the drawing]

Figure 4 shows an example of the circuit configuration of a digital phase-locked loop, Figure 2 shows an example of the circuit configuration of a Costanu loop, and Figure 3 shows an example of the circuit configuration of a Costanu loop.
The figure shows the frequency characteristics of a low-pass filter, Figure 4 shows an example of the configuration of a loop filter, Figure 5 shows a transient state of a control signal during phase synchronization, and Figure 6 shows a detailed example of the configuration of a loop filter. FIG. 1 is a diagram showing the transient state of the control signal during phase synchronization when the present invention is not used, FIG. 8 is a diagram when the present invention is used in the same state as FIG. 7, and FIG. 9 is a diagram showing the present invention. FIG. 10 is a time relationship diagram of each part for explaining the circuit configuration example of the loop filter in FIG. 11. 83, 86... Multiplication circuit, 13... Digital low pass filter, 15... Addition! , 16・
...Phase specification memory, 18...Sine wave generator, 21 and 21B...Phase comparator, 23Aj23B, 27...
LPF181, 112...MSB hold circuit, 91
...Rounding circuit.

Claims (1)

[Claims] 1. A circuit that specifies a certain phase, a circuit that outputs the value of a repetitive wave of the specified phase, a circuit that multiplies this output by an external input, and an output of this multiplication circuit. control the phase specifying circuit by calculating t-b''
1, a digital phase-locked loop having a filter having the characteristics as shown in FIG. A digital phase-locked loop characterized in that it has a circuit that causes the output signal of the memory to become an upper limit value in the case of an overflow of the lower limit, and a lower limit value in the case of an overflow of the lower limit.