JPS5917971B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5917971B2 JPS5917971B2 JP54056724A JP5672479A JPS5917971B2 JP S5917971 B2 JPS5917971 B2 JP S5917971B2 JP 54056724 A JP54056724 A JP 54056724A JP 5672479 A JP5672479 A JP 5672479A JP S5917971 B2 JPS5917971 B2 JP S5917971B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- metal layer
- gold
- titanium
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体基板と導電性支持板であるフレーム間の
付着強度及び抵抗接触のいずれをも同時に得ることを可
能にした半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that makes it possible to simultaneously obtain both adhesion strength and resistance contact between a semiconductor substrate and a frame that is a conductive support plate.
半導体装置は近年、安価に製造することが要求されてい
る。In recent years, semiconductor devices have been required to be manufactured at low cost.
そのため従来、半導体基板とフレーム間の接合には、半
導体基板と容易に比較的低温で共晶合金をつくり、しか
も、フレームヘのメッキ等による付着が容易な金等が用
いられてきた。しかし、金は貴金属で価格が高い為、従
来、安価な鉛、スズを主成分とする合金である半田が用
い5 られる様になつてきた。しかし半田は、半導体基
板には直接付着しない為、従来、半導体基板に対する付
着強度の大きなチタンやクロム等を半導体基板にあらか
じめ付着させ、一方、チタンやクロム等は半田との密着
性JOが悪い為、中間金属として、半田及びチタン、ク
ロム等のいずれに対しても密着力の大きなニッケルや銅
等をチタンやクロム等の上に付着させ、これにより半導
体基板とフレームとを密着するようにしている。Therefore, conventionally, for bonding between the semiconductor substrate and the frame, gold or the like has been used, which easily forms a eutectic alloy with the semiconductor substrate at a relatively low temperature, and which can be easily attached to the frame by plating or the like. However, since gold is a precious metal and is expensive, solder, which is an alloy mainly composed of inexpensive lead and tin, has come to be used5. However, since solder does not directly adhere to the semiconductor substrate, conventionally, titanium, chromium, etc., which have strong adhesion to the semiconductor substrate, are attached to the semiconductor substrate in advance.On the other hand, titanium, chromium, etc. have poor adhesion with solder, As an intermediate metal, nickel, copper, etc., which have strong adhesion to solder, titanium, chromium, etc., are deposited on top of titanium, chromium, etc., thereby making the semiconductor substrate and frame adhere closely. .
15ところが、チタンやクロムは半導体の不純物濃度が
小さくなると、半導体基板との間で抵抗接触を形成しな
くなる。15 However, when the impurity concentration of titanium and chromium in the semiconductor becomes low, they no longer form a resistive contact with the semiconductor substrate.
しかも半導体基板の一方の面に各種機能素子が熱拡散法
やイオンインフラ法等によつて形成されるが、この時、
電気的特性上、20半導体基板の不純物濃度は上記チタ
ンやクロム等の金属が抵抗接触しない程度のものを要求
する場合が多く、また、この半導体基板を基準電位にし
て使用する場合が多いものである。かかる様な場合は、
半導体基板の不純物濃度が低く抵抗率が高四 い為に発
生する基準電位の場所による変動を、半導体基板に接合
させたフレームが極めて低抵抗であり、半導体基板とフ
レームとが抵抗接触を有する事を利用して少なくしてい
た。しかし、半導体基板とフレームが抵抗接触を有しな
い場合には、30基準電位の場所による変動を起こし、
素子特性を変動あるいは不良としてしまう。第1図は従
来の半導体基板をフレームに密着させた一例の縦断面図
である。Moreover, various functional elements are formed on one side of the semiconductor substrate by thermal diffusion method, ion infrastructure method, etc.
Due to electrical characteristics, the impurity concentration of the 20 semiconductor substrate is often required to be such that the metals such as titanium and chromium mentioned above do not come into contact with each other, and this semiconductor substrate is often used with a reference potential. be. In such a case,
The frame bonded to the semiconductor substrate has an extremely low resistance, and the fact that the semiconductor substrate and the frame have resistive contact eliminates variations in the reference potential caused by the low impurity concentration and high resistivity of the semiconductor substrate. was used to reduce the amount. However, if the semiconductor substrate and the frame do not have resistive contact, the 30 reference potential will vary from place to place;
This causes the device characteristics to fluctuate or become defective. FIG. 1 is a longitudinal sectional view of an example of a conventional semiconductor substrate in close contact with a frame.
この従来例では、機能領域が形成された半導体基板1と
フレーム4土石 にメッキ等によつて付着させられた金
3の間に、金あるいは金合金2を置き加熱する事により
、半導体基板1とフレーム4とを接合している。:クー
J
この従米の方法では、高価な金属である金を用いている
為、半導体装置の価格力塙くなリ、また金あるいは金合
金等を用いて半導体基板1とフレーム4とを接合する為
、加熱温度が300℃以上と高く、半導体基板1上に形
成された機能領域が悪影響を受けるという問題がある。In this conventional example, gold or gold alloy 2 is placed between the semiconductor substrate 1 on which the functional area is formed and the gold 3 attached to the frame 4 by plating or the like, and is heated. It is joined to the frame 4. : Koo J In this conventional method, since gold, which is an expensive metal, is used, the price of semiconductor devices is not high, and the semiconductor substrate 1 and the frame 4 are bonded using gold or a gold alloy. Therefore, there is a problem that the heating temperature is as high as 300° C. or more, and the functional regions formed on the semiconductor substrate 1 are adversely affected.
また、該従来方法では、接合する際、半導体基板1の接
合面に出来たわずかな酸化膜等を除去しなければならな
いため、この接合面を機械的にこする等の作業が必要と
なる問題がある。In addition, in this conventional method, when bonding, it is necessary to remove a slight oxide film formed on the bonding surface of the semiconductor substrate 1, so there is a problem in that work such as mechanically rubbing the bonding surface is required. There is.
第2図は第1図に示された従来装置を改善した他の従来
装置を示す縦断面図である。FIG. 2 is a longitudinal sectional view showing another conventional device that is an improvement over the conventional device shown in FIG.
第2図に於いて、一方の主面に機能領域が形成された半
導体基板1の他方の主面に、真空蒸着法やスパツタリン
グ法等により、この半導体基板1との密着力の大きい金
属としてチタン5を付着させる。In FIG. 2, titanium, which is a metal with strong adhesion to the semiconductor substrate 1, is deposited on the other main surface of the semiconductor substrate 1 with a functional region formed on one main surface by vacuum evaporation, sputtering, or the like. Attach 5.
引き続き、半田との密着力の大きい金属としてニツケル
6を真空蒸着法やスパツタリング法等で付着させ、次に
半田7をフレーム4との間に置き加熱することにより、
半導体基板1とフレーム4とを接合する事が可能となる
。第2図に於ける従来装置は、第1図に於ける従来装置
の欠点を解消出来るものであるが、しかし第2図の従来
装置では新たに次の欠点が発生する。Subsequently, nickel 6, which is a metal with strong adhesion to solder, is attached by vacuum evaporation or sputtering, and then solder 7 is placed between it and the frame 4 and heated.
It becomes possible to bond the semiconductor substrate 1 and the frame 4 together. Although the conventional device shown in FIG. 2 can eliminate the drawbacks of the conventional device shown in FIG. 1, the following new drawbacks occur in the conventional device shown in FIG.
半導体基板1の機能領域は、この半導体基板1に各種不
純物を熱拡散法やイオン注入法等により導入する事によ
リ形成するものである為、この半導体基板1の不純物濃
度は小さい。一方、チタンは不純物濃度の小さい半導体
基板に対してシヨツトキ接合をする事は周知の事実であ
り、従つて上記チタン5と半導体基板1とは非抵抗接触
となつてしまう.この為、半導体基板1を基準電位にし
て、機能領域を動作させる場合、金属であるフレーム4
の電気抵抗が極めて小さい事を利用し、フレーム4と半
導体基板の機能領域を形成した面と反対側の面とを接合
し、これによりフレーム4と半導体基板1とが抵抗接触
となれば、半導体基板1を一定基準電位に保つ事が可能
となる。Since the functional regions of the semiconductor substrate 1 are formed by introducing various impurities into the semiconductor substrate 1 by thermal diffusion, ion implantation, etc., the impurity concentration of the semiconductor substrate 1 is small. On the other hand, it is a well-known fact that titanium forms a shot contact with a semiconductor substrate having a low impurity concentration, and therefore the titanium 5 and the semiconductor substrate 1 are in non-resistance contact. For this reason, when operating the functional area with the semiconductor substrate 1 at a reference potential, the metal frame 4
Taking advantage of the fact that the electrical resistance of It becomes possible to maintain the substrate 1 at a constant reference potential.
しかし、フレーム4と半導体基板1とが非抵抗接触とな
つた場合、半導体基板1の不純物濃度が小さい為、半導
体基板1の抵抗が高くなり、従つて、その非抵抗接触の
為、電流は半導体基板中を流れる事により電位差が生じ
、半導体基板が一様傷に基準電位にならなくなク、この
半導体基板の基準電位の変動により、機能領域は正常な
動作をしなくなる。However, when the frame 4 and the semiconductor substrate 1 are in non-resistance contact, the resistance of the semiconductor substrate 1 becomes high because the impurity concentration of the semiconductor substrate 1 is low, and therefore, due to the non-resistance contact, the current flows through the semiconductor substrate 1. A potential difference is generated by the flow in the substrate, and the semiconductor substrate is not at a reference potential due to uniform scratches, and due to fluctuations in the reference potential of the semiconductor substrate, the functional area does not operate normally.
本発明は上記のような従来のものの問題点を解消するた
めになされたもので、半田等を用いて安価に半導体基板
と導電性支持板とを接合するようにした半導体装置にお
いて、半導体基板の機能領域が形成されていない他方の
主面に、該基板との間に抵抗接触を有する第1の金属層
を設け、該第1の金属層及び上記基板の他方の主面上に
半導体基板との付着強度の大きい第2の金属層を設け、
さらに該第2の金属層上にこれを半田を介して上記導電
性支持フレームに接着する第3の金属層を設けることに
より、半導体基板と導電性支持板との半田を用いた密着
性を向上でき、かつ半導体装置と導電性支持板との間を
抵抗接触とすることができる半導体装置を提供すること
を目的としている。The present invention has been made in order to solve the problems of the conventional devices as described above, and provides a semiconductor device in which a semiconductor substrate and a conductive support plate are bonded together at low cost using solder or the like. A first metal layer having resistive contact with the substrate is provided on the other main surface on which the functional region is not formed, and a semiconductor substrate is provided on the first metal layer and the other main surface of the substrate. providing a second metal layer with a high adhesion strength;
Further, by providing a third metal layer on the second metal layer, which is bonded to the conductive support frame via solder, the adhesion between the semiconductor substrate and the conductive support plate using solder is improved. It is an object of the present invention to provide a semiconductor device which is capable of forming a resistive contact between the semiconductor device and a conductive support plate.
以下、本発明の実施例を図について説明する。Embodiments of the present invention will be described below with reference to the drawings.
第3図は本発明の一実施例による半導体基板とフレーム
とを接着させた状態を示す縦断面図である。第3図に於
いて、第1図および第2図と同一符号は同一又は相当部
分を示し、本実施例では、機能領域が形成された半導体
基板1と銅合金等により成るフレーム4とを鉛、スズ等
の合金である半田7で接着する為?、まず半導体基板1
の機能領域の形成された主面と反対の主面、即ちフレー
ム4と接着する面にあらかじめ金8を10−400オン
グストローム(λ)真空蒸着法あるいはスパツタリング
法で付着させ、引き続きチタン5を同じく真空蒸着法あ
るいはスパツタリング法で100〜5000人好ましく
は300〜1000λ付着させ、更に引き続きニツケル
6を真空蒸着法あるいはスパッタリング法で300〜5
00人好ましくは500〜1500人付着させる。次に
上記の金8、チタン5およびニツケル6の付着した半導
体基板1とフレーム4との間に半田7をはさみ、これを
150〜300℃に加熱する。するとこれにより半導体
基板1をフレーム4に接着する事が可能となる。本実施
例では、金8の膜厚を10〜100λとしたので、金8
は全面に均一な膜とはならずに島状に付着する事は周知
の事実である。FIG. 3 is a longitudinal sectional view showing a state in which a semiconductor substrate and a frame are bonded together according to an embodiment of the present invention. In FIG. 3, the same reference numerals as in FIGS. 1 and 2 indicate the same or corresponding parts, and in this embodiment, the semiconductor substrate 1 on which the functional area is formed and the frame 4 made of copper alloy or the like are , to bond with solder 7, which is an alloy such as tin? , first the semiconductor substrate 1
Gold 8 with a thickness of 10-400 angstroms (λ) is deposited in advance on the main surface opposite to the main surface on which the functional area is formed, that is, the surface to be bonded to the frame 4, by vacuum evaporation or sputtering, and then titanium 5 is deposited in the same vacuum. 100 to 5,000 people, preferably 300 to 1,000 λ, are deposited by vapor deposition or sputtering, and then 300 to 5 λ of nickel 6 is deposited by vacuum evaporation or sputtering.
00 people, preferably 500 to 1500 people. Next, solder 7 is sandwiched between the frame 4 and the semiconductor substrate 1 to which the gold 8, titanium 5, and nickel 6 have been adhered, and this is heated to 150 to 300°C. This makes it possible to bond the semiconductor substrate 1 to the frame 4. In this example, since the film thickness of gold 8 was set to 10 to 100λ,
It is a well-known fact that the film does not form a uniform film over the entire surface, but instead adheres in the form of islands.
従つて、チタン5はその一部は半導体基板1と、残りの
部分は金8と接着される事となる。この為、半導体基板
1の不純物濃度が小さく、チタン5とシヨツトキ接合を
生じた場合でも、半導体基板1とチノン5の間に存在す
る金8の為、該金8の部分ではシヨツトキ接合は生じな
い。Therefore, part of the titanium 5 is bonded to the semiconductor substrate 1, and the remaining part is bonded to the gold 8. Therefore, even if the impurity concentration of the semiconductor substrate 1 is low and a shot junction occurs with the titanium 5, the shot junction will not occur in the gold 8 part because the gold 8 exists between the semiconductor substrate 1 and the chinon 5. .
この為、チタン5と半導体基板1とが接着した部分は、
シヨツトキ接合となり非抵抗接触であつたとしても、金
8と半導体基板1とが接着した部分は抵抗接触となる。
また、半導体基板1一金8−チタン5の順で接着した部
分は密着力は弱いが、半導体基板1−チタン5の順で接
着した部分の密着力は極めて強い事は周知の事実である
。これらの結果、本実施例では、半導体基板1とチタン
5とは、金8の膜厚を10〜100Kとしたので、抵抗
接触を有し、かつ密着力の強いものとなる.また、鉛、
スズ等の合金である半田7はチタン5と接着しないが、
本実施例では半田7及びチタン5のいずれにも接着する
ニツケル6を介在せしめたので、半導体基板1とフレー
ム4とを抵抗接触を有し、かつ強い密着力で接着する事
が可能となる。Therefore, the part where titanium 5 and semiconductor substrate 1 are bonded is
Even if the contact is non-resistance due to a shot bond, the portion where the gold 8 and the semiconductor substrate 1 are bonded becomes a resistance contact.
Further, it is a well-known fact that the adhesion of the part where the semiconductor substrate 1, gold 8 and titanium 5 are bonded in this order is weak, but the adhesion of the part where the semiconductor substrate 1 and titanium 5 are bonded in this order is extremely strong. As a result, in this example, the semiconductor substrate 1 and the titanium 5 have a resistive contact and strong adhesion since the gold 8 has a thickness of 10 to 100K. Also, lead,
Solder 7, which is an alloy such as tin, does not adhere to titanium 5, but
In this embodiment, since the nickel 6 that adheres to both the solder 7 and the titanium 5 is interposed, the semiconductor substrate 1 and the frame 4 can be bonded to each other with resistance contact and strong adhesion.
また、半田7を用いたので、150〜300℃の温度で
半導体基板1とフレーム4とを接着でき、半導体基板1
上の機能領域に悪影響を及ぽすこともない。なお、上記
実施例では金8の膜厚を10〜100人にする事により
金8が島状に付着する事を利用したが、本発明では、金
8を100K以上付着した後、写真蝕刻技術を用い、そ
の一部を選択的に除去して金8を島状とし、しかる後、
チタン6を蒸着法あるいはスパッタリング法等で付着さ
せても同一の効果を有する。Further, since the solder 7 is used, the semiconductor substrate 1 and the frame 4 can be bonded together at a temperature of 150 to 300°C, and the semiconductor substrate 1
There is no negative impact on the functional areas above. In the above embodiment, the film thickness of gold 8 was set to 10 to 100 mm to make use of the fact that gold 8 was deposited in an island shape. However, in the present invention, after depositing gold 8 of 100K or more, photolithography was applied. Using a method, a part of the gold 8 is selectively removed to form islands, and then,
The same effect can be obtained even if titanium 6 is deposited by vapor deposition, sputtering, or the like.
また、上記の実施例では、第1の金属層として金8を用
いたが、この第1の金属は半導体基板1と抵抗接触を有
する他の金属、例えば銀でもよく、このようにしても上
記実施例と同様の効果を奏する。Further, in the above embodiment, gold 8 is used as the first metal layer, but this first metal may be other metal, such as silver, which has a resistive contact with the semiconductor substrate 1. The same effects as in the embodiment are achieved.
さらにまた、上記実施例では、第2の金属層としてチタ
ン5を用いたが、この第2の金属は半導体基板1に対し
密着力の強い金属、例えば、クロムを用いてもよく、こ
のようにしても上記実施例と同様な効果を有する。また
、本発明の原理を用いれば、半導体基板1に付着させる
金8の量を制御する事によりシヨツトキ接合と抵抗接触
との中間の任意の特性の素子を形成させる事も可能とな
る。Furthermore, in the above embodiment, titanium 5 is used as the second metal layer, but the second metal may be a metal that has strong adhesion to the semiconductor substrate 1, such as chromium. However, the same effect as in the above embodiment can be obtained. Further, by using the principles of the present invention, by controlling the amount of gold 8 deposited on the semiconductor substrate 1, it is possible to form an element with arbitrary characteristics between a shot junction and a resistive contact.
以上のように、本発明に係る半導体装置によれば、半導
体基板の機能領域が形成されていない他方の主面に、該
基板との間に抵抗接触を有する第1の金属層を設け、該
第1の金属層及び上記基板の他方の主面上に半導体基板
との付着強度の大きい第2の金属層を設け、さらに該第
2の金属層上にこれを半田を介して導電性支持板に接着
する第3の金属層を設けたので、従米の製造方法に大き
な変更を加える事なく従来より安価で、半導体基板と導
電性支持板の密着力を大きく向上でき、かつ抵抗接触を
得ることができる効果がある。As described above, according to the semiconductor device of the present invention, the first metal layer having resistance contact with the semiconductor substrate is provided on the other main surface on which the functional region is not formed, and A second metal layer having a high adhesion strength to the semiconductor substrate is provided on the first metal layer and the other main surface of the substrate, and is further bonded onto the second metal layer via solder to a conductive support plate. By providing a third metal layer that adheres to the semiconductor substrate, it is possible to significantly improve the adhesion between the semiconductor substrate and the conductive support plate at a lower cost than before without making any major changes to the manufacturing method, and to obtain a resistive contact. It has the effect of
第1図は従米の半導体装置を示す縦断面図、第2図は改
良された従来の半導体装置を示す縦断面図、第3図は本
発明の一実施例による半導体装置の縦断面図である。
図中の同一符号は同一のものをあられす。1・・・半導
体基板、4・・・導電性支持板、(フレーム5・・・第
2の金属層(チタン)、6・・・第3の金属層(ニツケ
ル)、7・・・半田、8・・・第1の金属層(至)。FIG. 1 is a vertical cross-sectional view showing a conventional semiconductor device, FIG. 2 is a vertical cross-sectional view showing an improved conventional semiconductor device, and FIG. 3 is a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention. . The same symbols in the figures refer to the same items. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 4... Conductive support plate, (Frame 5... Second metal layer (titanium), 6... Third metal layer (nickel), 7... Solder, 8...First metal layer (to).
Claims (1)
他方の主面が上記導電性支持板に接着される半導体基板
と、該半導体基板の他方の主面に部分的に設けられ該半
導体基板との間に抵抗接触を有する第1の金属層と、上
記半導体基板の他方の主面及び上記第1の金属層上に設
けられ該半導体基板に対する付着強度が大きい第2の金
属層と、該第2の金属層を半田を介して上記導電性支持
板に接着するための第3の金属層とを備えたことを特徴
とする半導体装置。 2 上記第1の金属層は、金あるいは銀であり、上記第
2の金属層は、チタンあるいはクロムであることを特徴
とする特許請求の範囲第1項記載の半導体装置。[Scope of Claims] 1. A conductive support plate, a semiconductor substrate having a functional area formed on one main surface and bonded to the conductive support plate on the other main surface, and a semiconductor substrate on the other main surface of the semiconductor substrate. a first metal layer that is partially provided and has resistance contact with the semiconductor substrate; and a first metal layer that is provided on the other main surface of the semiconductor substrate and the first metal layer and has a high adhesion strength to the semiconductor substrate; A semiconductor device comprising: a second metal layer; and a third metal layer for bonding the second metal layer to the conductive support plate via solder. 2. The semiconductor device according to claim 1, wherein the first metal layer is gold or silver, and the second metal layer is titanium or chromium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54056724A JPS5917971B2 (en) | 1979-05-04 | 1979-05-04 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54056724A JPS5917971B2 (en) | 1979-05-04 | 1979-05-04 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55146940A JPS55146940A (en) | 1980-11-15 |
| JPS5917971B2 true JPS5917971B2 (en) | 1984-04-24 |
Family
ID=13035433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54056724A Expired JPS5917971B2 (en) | 1979-05-04 | 1979-05-04 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917971B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206035A (en) * | 1981-06-12 | 1982-12-17 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
-
1979
- 1979-05-04 JP JP54056724A patent/JPS5917971B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55146940A (en) | 1980-11-15 |
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