JPS5917972B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an electrode extraction structure for a high power semiconductor device.

As is well known, in semiconductor devices for high power use, the diameter of the wafer becomes large, and when metal electrodes are soldered onto both sides of the wafer, as in semiconductor devices for medium to low power use, the wafer and metal electrodes become disconnected. V) There is a risk that the wafer itself may be damaged due to the difference in the coefficient of thermal expansion. For this reason, in this type of high-power semiconductor device, metal electrodes are generally pressure-bonded to both or one side of the wafer to compensate for misalignment due to differences in thermal expansion coefficients. FIG. 1 shows a conventional example of this type of flat high-power semiconductor device.

In FIG. 1, each main surface of the silicon wafer 1 has
Aluminum layer 2 to make ohmic contact
is formed, and there is a molybdenum plate 3 that also serves as reinforcement at the bottom.
10 molybdenum plates 4 are interposed on the upper part to release thermal distortion and stress, and these are pressed together by a copper block 5. In the above configuration, when the semiconductor device is energized, it will be in the same state as when a thermal cycle is applied, and when the thermal expansion coefficient of each member metal is 15 when silicon is 1, molybdenum is approximately twice that, and copper is approximately Since it is 6 times larger, a slat-like movement occurs at the pressure contact surface between the upper aluminum layer 2 and the molybdenum plate 4, as shown in an enlarged view in FIG.

That is, the surface roughness of the molybdenum plate 4 is 3 to 5μ at most (V), and the surface of the molybdenum plate 4 and the surface of the aluminum layer 2 are different from each other due to distortion of the silicon wafer 1 or the molybdenum plate 4 itself. Therefore, the surface of the aluminum layer 2 is exposed to air, and the surface of the aluminum layer 2 is not evenly contacted.
The stable oxide film 2a has a thickness of about 00 to 5000 λ25.

Therefore, when such a slicing motion occurs between each surface as described above and continues, the current will become more concentrated in the area where the contact resistance is small, and the alloying of aluminum and molybdenum will occur as shown by reference numeral 6. 30, the forward voltage drop of the device fluctuates from the initial value ν, and cracks occur in the silicon in areas where alloying has progressed. In fact, according to the experience of the inventors, it has been observed that the forward voltage drop fluctuates by about 0.5V after 50 hours of energization, and cracks occur in the silicon35. Although the cause of this has not yet been thoroughly investigated, it is presumed to be due to the presence of an oxide film on the surface of the aluminum layer and insufficient escape of thermal strain, as described above. In order to eliminate such drawbacks of the conventional technology, this invention forms a metal layer, which is a hard metal that does not easily oxidize, on the surface of the aluminum layer, and a silver plate is placed between the molybdenum plate and the silver plate. The plate makes it easier to absorb stress.

Hereinafter, an embodiment of a semiconductor device according to the present invention will be described.
This will be explained in detail with reference to FIG.

In FIG. 3, an aluminum layer 2 of about 10 to 20 μm is formed on the main surface of a silicon wafer 1 by vapor deposition in the same manner as described above, and then, since rhodium plating cannot be applied on aluminum, commercially available zincate is first applied. A copper flash layer 8 of about 0.2 to 0.5 μm is used as a base to form a zinc layer 7 substituted by the treatment solution and to improve adhesion between zinc and zinc, and then this copper flash layer is A dinium layer 9 of about 0.3 to 0.8 μm is formed on the surface of the substrate 8 by plating. According to experiments conducted by the inventors, it has been confirmed that without the underlying copper flash layer 8, the adhesion of the dielectric layer 9 is poor, and if the diminium layer 9 is formed over 2 μm, cracks occur in the diminium layer 9. Subsequently, a silver plate 10 is placed on the zinc layer 9, and then the molybdenum plate 4 and the copper block 5 are pressed together.

Here, if the molybdenum plate 4 were brought into direct contact with the rhodium layer 9, the silver plate 10 would cause cracks in the rhodium layer 9 or the silicon wafer 1 due to the slat-like movement. ) or distortion of the molybdenum plate 4 from being applied to this contact surface. Furthermore, according to experiments conducted by the inventors, the silver plate 10 cannot absorb the above-mentioned stress or strain when the thickness is less than 100 μm, and when the thickness exceeds 300 μm, its coefficient of thermal expansion is about 10 times that of silicon. However, the effect of thermal expansion was undesirable. Note that instead of the copper flash layer 8 described above, a nickel plating layer with a thickness of 0.5 to 1
Even if it is formed to a thickness of about μ, similar actions and effects can be obtained. As detailed above, according to the present invention, since the dielectric layer is formed on the main surface of the wafer, the surface is hard and oxidizable, and there is a predetermined thickness between the diminium layer and the molybdenum plate. Because it is covered with silver plates,
There is an advantage that warping of silicon wafers and distortion of molybdenum plates caused by differences in thermal expansion coefficients caused by thermal cycles during energization can be effectively absorbed. It was confirmed that there was no change in the forward voltage drop and no cracking occurred in the silicon wafer even after 5,000 hours had passed since the start.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the main part configuration of a conventional flat high-power semiconductor device, FIG. 2 is an enlarged explanatory view of the same main part, and FIG.
The figure is an enlarged cross-sectional view showing the main structure of a flat high-power semiconductor device to which an embodiment of the present invention is applied. 1... Silicon wafer 2... Aluminum layer 3, 4... Molybdenum plate, 5...
...Copper block, 7...Zinc layer, 8...
・Copper flash layer, 9...Dinium layer, 10
・・・・・・Silver plate.

Claims (1)

[Claims] 1. A first layer of aluminum, a second layer of zinc, and a third layer of copper or nickel on at least one main surface of the semiconductor substrate.
layer, a fourth layer of rhodium is sequentially formed, and a molybdenum plate is superimposed on the fourth layer with a silver plate interposed therebetween,
A semiconductor device characterized in that the molybdenum plate is loaded to take out the electrode on the main surface. 2. The semiconductor device according to claim 1, wherein the fourth layer of rhodium has a thickness in the range of 0.3 to 0.8 μm. 3. The semiconductor device according to claim 1, wherein the thickness of the silver plate is in the range of 100 to 300 μm.