JPS5917973B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5917973B2 JPS5917973B2 JP54156500A JP15650079A JPS5917973B2 JP S5917973 B2 JPS5917973 B2 JP S5917973B2 JP 54156500 A JP54156500 A JP 54156500A JP 15650079 A JP15650079 A JP 15650079A JP S5917973 B2 JPS5917973 B2 JP S5917973B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- aluminum layer
- plate
- molybdenum
- molybdenum plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置、特に大電力用の半導体装置の電
極取り出し構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly an electrode extraction structure for a high power semiconductor device.
周知のように大電力用の半導体装置ではウエ・・の径も
大きくなつて、中、小電力用の半導体装置のように、ウ
ェハの両面に金属電極をハンダなどでロー付けすると、
ウェハと金属電極との熱膨張係数の相違により、ウェハ
自体が破損する惧れがある。このためにこの種の大電力
用半導体装置では、一般にウェハの両面あるいは片面に
金属電極を圧接構造として、熱膨張係数の相違からくる
ずれを補償するようにしている。第1図にこの種の平形
大電力用半導体装置の従来例を示してある。As is well known, in semiconductor devices for high power, the diameter of the wafer becomes large, and when metal electrodes are soldered on both sides of the wafer, as in semiconductor devices for medium to low power,
Due to the difference in thermal expansion coefficient between the wafer and the metal electrode, there is a risk that the wafer itself may be damaged. For this reason, in this type of high-power semiconductor device, metal electrodes are generally pressure-bonded to both or one side of the wafer to compensate for misalignment due to differences in thermal expansion coefficients. FIG. 1 shows a conventional example of this type of flat high-power semiconductor device.
この第1図において、シリコンウェハ1の各主面には、
オーミックコンタクトをとるために、アルミニウム層2
、2が形成されており、下部に補強を兼ねたモリブデン
板3をロー付けすると共に、上部に熱歪み、応力を逃が
すためのモリブデン板4を介在させ、これらを銅プ5
ロック5、5により圧接構造としたものである。前記構
成において、この半導体装置に通電すると、熱サイクル
を加えたのと同様の状態になD)各部材金属の熱膨張係
数が、シリコンを1としたとき、モリブデンは約2倍、
銅は約6倍であるた0 めに、上部のアルミニウム層2
とモリブデン板4との圧接面において、第2図に拡大し
て示したようにスリコギ状の運動を生ずる。すなわち、
前記モリブデン板4の表面粗さはせいぜい3〜5μであ
V、かつこのモリブデン板45の面とアルミニウム層2
の面とは、シリコンウェハ1やモリブデン板4自体の歪
みなどのために均一に接触されてはおらず、このために
前記したようにスリコギ状の運動が続けられると、接触
抵抗の小さい部分には益々電流が集中し、かつアルミ!
0 ニウムとモリブデンの合金化が符号6で示すように
進み、装置の順方向電圧降下が初期値から変動したヤ、
合金化の進んだ部分のシリコンに割れを生ずる。In FIG. 1, each main surface of the silicon wafer 1 has
Aluminum layer 2 to make ohmic contact
.
The locks 5, 5 form a press-contact structure. In the above configuration, when the semiconductor device is energized, it becomes in the same state as when a thermal cycle is applied. D) When the coefficient of thermal expansion of each component metal is 1 for silicon, the coefficient of thermal expansion for molybdenum is approximately twice that.
Copper is about 6 times more expensive, so the upper aluminum layer 2
At the pressure contact surface between the molybdenum plate 4 and the molybdenum plate 4, a slat-like movement occurs as shown in an enlarged view in FIG. That is,
The surface roughness of the molybdenum plate 4 is at most 3 to 5μ, and the surface roughness of the molybdenum plate 45 and the aluminum layer 2 are
Due to the distortion of the silicon wafer 1 and the molybdenum plate 4 themselves, the surface is not in uniform contact with the surface of More and more current is concentrated, and aluminum!
0 Alloying of Ni and molybdenum progresses as shown by code 6, and the forward voltage drop of the device fluctuates from its initial value.
Cracks occur in silicon in highly alloyed areas.
実際に発明者らの経験によると、通電50時間で順方向
電圧降下がO、IV程度変動し、6 かつシリコンに割
れを生ずることが認められた。この原因としては未だよ
く調べられていないが、前記したようにシリコンウェハ
のキpとか歪み、モリブデン板の表面粗さ、モリブデン
とアルミニウムとが合金し易い金属であること、および
歪み30の逃げの不充分さによるもめと推定される。こ
の発明は従来のこのような欠点を除去する目的で、半導
体基体主面のアルミニウム層とモリブデン板のアルミニ
ウム層との間に、まず銅フラッシュメッキ層、ついでロ
ジユウムメツキ層を各々35両面に形成した銀板を介在
して敷き込み、この構成によつて熱サイクルによつて生
ずる応力、歪みを吸収し易くしたものである。以下、こ
の発明に係わる半導体装置の一実施例につき、第3図を
参照して詳細に説明する。In fact, according to the experience of the inventors, the forward voltage drop fluctuates by about 0.5V after 50 hours of energization, and it has been observed that cracks occur in the silicon. The causes of this have not yet been well investigated, but as mentioned above, the cracks and distortion of the silicon wafer, the surface roughness of the molybdenum plate, the fact that molybdenum and aluminum are metals that easily alloy, and the release of distortion 30. It is presumed that the dispute was due to insufficiency. In order to eliminate such drawbacks of the conventional method, the present invention has developed a silver plated film in which a copper flash plating layer and then a rhodium plating layer are formed between the aluminum layer on the main surface of the semiconductor substrate and the aluminum layer of the molybdenum plate on both sides. A plate is interposed between the layers, and this structure makes it easier to absorb stress and distortion caused by thermal cycles. Hereinafter, one embodiment of a semiconductor device according to the present invention will be described in detail with reference to FIG.
この第3図において、この実施例では銀板7を用い、こ
の銀板7の両面に、まずメツキによつて0.2〜0.5
μ程度の銅フラツシユ層8を形成したのち、この銅フラ
ツシユ層8を下地として、同様にメツキによV)0,3
〜0,8μ程度の口ジニウム層9を形成させる。発明者
らの実験によると、下地銅フラツシユ層8がないと、口
ジニウム層9の密着性が悪く、またロジ ウム層9を2
μ以上形成させると、この口ジニウムにクラツクの入る
ことが確認された。そしてまた前記シリコンウエハ1の
主面上に蒸着によつて10〜20μ程度形成されたアル
ミニウム層2と同様に、前記モリブデン板4の面にもま
た5〜10μ程度のアルミニウム層10を形成させ、こ
れらのアルミニウム層2,10間に前記のように処理さ
れた銀板7を介在させて敷き込み、これらを圧接させる
のである。ここで前記モリブデン板4にアルミニウム層
2を形成させたのは、このモリブデン板4が直接口ジニ
ウム層9に接したのでは、前記スリコギ状の運動によつ
て、この口ジニウム層9にクラツクを生じて了うからで
あり、また前記銀板7はその厚さが100μ以下ではシ
リコンウエハのそりとかモリブデン板の歪みを吸収でき
ず、かつ300μ以上になるとその熱膨張係数がシリコ
ンの約10倍であるために、外部に熱膨張の影響があら
れれて好ましくない。以上詳述したようにこの発明によ
るときは、半導体基体主面のアルミニウム層とモリブデ
ン板のアルミニウム層との間に、銅フラツシユメツキ層
を介して口ジニウムメッキ層を両面に形成した銀板を敷
き込んで圧接構造としてあるため、通電時の熱サイクル
によつて生ずる応力、歪みなどを効果的に吸収できる利
点があり、実際上、この発明を適用した半導体装置では
、通電開始よV)5000時間を経ても、順方向電圧降
下の変動がない、かつシリコンウエハに割れなども生じ
ないことを確認し得たものである。In FIG. 3, a silver plate 7 is used in this embodiment.
After forming a copper flash layer 8 of about μ, using this copper flash layer 8 as a base, plating is performed in the same manner as V)0,3.
A layer 9 of about 0.8 μm is formed. According to experiments conducted by the inventors, without the base copper flash layer 8, the adhesion of the rhodium layer 9 is poor, and the rhodium layer 9 is
It has been confirmed that cracks occur in this dianium when it is formed more than μ. Similarly to the aluminum layer 2 formed on the main surface of the silicon wafer 1 by vapor deposition of about 10 to 20 μm, an aluminum layer 10 of about 5 to 10 μm is also formed on the surface of the molybdenum plate 4. The silver plate 7 treated as described above is placed between these aluminum layers 2 and 10, and these are brought into pressure contact. The reason why the aluminum layer 2 is formed on the molybdenum plate 4 is that if the molybdenum plate 4 was in direct contact with the aluminum layer 9, it would not be possible to crack the aluminum layer 9 by the slicing motion. Moreover, if the thickness of the silver plate 7 is less than 100 μm, it cannot absorb the warping of the silicon wafer or the distortion of the molybdenum plate, and if the thickness is more than 300 μm, its coefficient of thermal expansion is about 10 times that of silicon. Therefore, the outside is affected by thermal expansion, which is undesirable. As described in detail above, according to the present invention, a silver plate having a zinc plating layer formed on both sides is laid between the aluminum layer on the main surface of the semiconductor substrate and the aluminum layer of the molybdenum plate with a copper flashing layer interposed therebetween. Because it has a press-contact structure, it has the advantage of effectively absorbing stress, distortion, etc. caused by thermal cycles during energization, and in practice, in a semiconductor device to which this invention is applied, it is possible to effectively absorb stress and strain caused by thermal cycles during energization. It was also confirmed that there was no change in the forward voltage drop and that no cracks occurred in the silicon wafer.
第1図は従来例による平形大電力用半導体装置の要部構
成を示す断面図、第2図は同上要部の拡大説明図、第3
図はこの発明の一実施例を適用した平形大電力用半導体
装置の要部構成を示す断面図である。
1・・・シリコンウエハ、2・・・アルミニウム層、3
4・・・モリブデン板、5・・・銅プロツク、7・・・
銀板、8・・・銅フラツシユ層、9・・・口ジニウム層
。FIG. 1 is a cross-sectional view showing the main part configuration of a conventional flat high-power semiconductor device, FIG. 2 is an enlarged explanatory view of the same main part, and FIG.
The figure is a sectional view showing the main part configuration of a flat high power semiconductor device to which an embodiment of the present invention is applied. 1... Silicon wafer, 2... Aluminum layer, 3
4... Molybdenum plate, 5... Copper block, 7...
Silver plate, 8...Copper flash layer, 9...Dinium layer.
Claims (1)
ミニウム層と、これに対向させたモリブデン板のアルミ
ニウム層との間に対して、銅の第1層、ロジユウムの第
2層を各々両面に形成した厚さ100〜300μ範囲の
銀板を介在させ、かつ前記モリブデン板に加重して、前
記主面の電極を取り出したことを特徴とする半導体装置
。1. A first layer of copper and a second layer of rhodium were formed on both sides between the aluminum layer formed on at least one main surface of the semiconductor substrate and the aluminum layer of the molybdenum plate opposed thereto. A semiconductor device characterized in that the electrodes on the main surface are taken out by interposing a silver plate having a thickness in the range of 100 to 300 μm and applying weight to the molybdenum plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54156500A JPS5917973B2 (en) | 1979-11-30 | 1979-11-30 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54156500A JPS5917973B2 (en) | 1979-11-30 | 1979-11-30 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5679440A JPS5679440A (en) | 1981-06-30 |
| JPS5917973B2 true JPS5917973B2 (en) | 1984-04-24 |
Family
ID=15629112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54156500A Expired JPS5917973B2 (en) | 1979-11-30 | 1979-11-30 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917973B2 (en) |
-
1979
- 1979-11-30 JP JP54156500A patent/JPS5917973B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5679440A (en) | 1981-06-30 |
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