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JPS5917978B2 - Manufacturing method of semiconductor device - Google Patents
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JPS5917978B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5917978B2
JPS5917978B2 JP53145914A JP14591478A JPS5917978B2 JP S5917978 B2 JPS5917978 B2 JP S5917978B2 JP 53145914 A JP53145914 A JP 53145914A JP 14591478 A JP14591478 A JP 14591478A JP S5917978 B2 JPS5917978 B2 JP S5917978B2
Authority
JP
Japan
Prior art keywords
plating
manufacturing
semiconductor device
conductor
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53145914A
Other languages
Japanese (ja)
Other versions
JPS5571033A (en
Inventor
雅信 小原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53145914A priority Critical patent/JPS5917978B2/en
Publication of JPS5571033A publication Critical patent/JPS5571033A/en
Publication of JPS5917978B2 publication Critical patent/JPS5917978B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特に絶縁フィルム上に
導体細条のパターンを有する半導体装置用基板の製造方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a substrate for a semiconductor device having a pattern of conductive strips on an insulating film.

近年、時計、電卓、計算機等に用いられている半導体装
置は、小型化、高信頼度化、低製造コスト化のため、従
来のセラミック、金属フレームに金、アルミ細線を用い
て半導体素子をボンディングする方法に代つて、 Au
、Sn等をメッキした5Cu等の導体細条を有するポリ
イミド、ポリエステル樹脂等の有機材で形成された可撓
性の絶縁フィルム状の基板(以後キャリアテープと言ラ
)に同時ボンディングによVi半導体素子をボンディン
グする方法が多く使用されてきている。
In recent years, semiconductor devices used in watches, calculators, calculating machines, etc. are made smaller, more reliable, and lower in manufacturing cost by bonding semiconductor elements to conventional ceramic or metal frames using thin gold or aluminum wires. Instead of the method of Au
, a Vi semiconductor by simultaneous bonding to a flexible insulating film-like substrate (hereinafter referred to as carrier tape) made of an organic material such as polyimide or polyester resin having conductor strips such as 5Cu plated with Sn, etc. Many methods of bonding devices have been used.

10このキヤサアテープは、第1図にその一例を要部斜
視図で示すように35Iltm等の一定の幅にスリット
し、かつその両側にスプロケット孔1aおよび中央部に
半導体素子を接続させる孔Ib、Icが形成された絶縁
フィルム1上にパターニングさ15れかつその表面VC
Au、Sni半田等のメッキを施したCu等の導体細条
2とから形成されている。
10 As shown in FIG. 1, an example of which is a perspective view of the main part, this carrier tape is slit to a certain width such as 35Iltm, and has sprocket holes 1a on both sides and holes Ib and Ic in the center for connecting semiconductor elements. is patterned on the insulating film 1 on which VC is formed.
It is formed from conductor strips 2 made of Cu or the like plated with Au, Sni solder or the like.

このように構成されたキャリアテープは、半導体素子の
ボンディングおよび半導体素子がボンディングされた導
体線条2の一部を時計、電卓計算20機等の装置に接続
する個所の信頼性を高めるために一般には導体細条2の
メッキにAu電解メッキが用いられている。そして、従
来このキャリアテープの製造方法は、第2図に要部断面
図で示したように必要な孔1a、1b、Icを打抜いた
絶縁25フィルム1に約35μmの厚さのCu箔を貼り
付け、その表面に写真製版により細条をパターニングし
、そのパターンにCuの不要部分をエッチング除去して
細条素地2aを形成し、その後この表面に電解によl!
)Auメッキを施し、 Auメッキ層302bを設ける
方法によつて形成されている。しかしながら、上記従来
の製造方法によると。導体細条2の表面全面にAuメッ
キ層2bが形成され、さらに第3図に要部平面図に示す
ように電解メッキ用の導電配線3に全ての導体細条2を
接35続しなくてはならない制約があるため、半導体素
子のボンディング部分の導通チェックができないなどの
欠点を有していた。したがつて.本発明の目的は上記従
来の製造方法の欠点を除去するためになされたものであ
り、導体細条を形成するに際し,導体素地上に導体細条
のパターン状に素地のエツチングに対して耐蝕性を有す
る金属のメツキを施し、その上面にAuメツキを行い、
このAuメツキ層をマス.クにして素地をパターニング
するようにした半導体装置の製造方法を提供することを
目的としている。
The carrier tape constructed in this way is generally used to improve the reliability of the bonding of semiconductor elements and the connection of a part of the conductor wire 2 to which the semiconductor elements are bonded to devices such as watches and calculators. In this case, Au electrolytic plating is used for plating the conductor strips 2. The conventional manufacturing method for this carrier tape is to attach a Cu foil with a thickness of about 35 μm to an insulating film 1 in which necessary holes 1a, 1b, and Ic are punched out, as shown in the cross-sectional view of the main part in FIG. After pasting, thin strips are patterned on the surface by photolithography, unnecessary portions of Cu are etched away in the pattern to form a thin strip base 2a, and then this surface is electrolytically coated with l!
) is formed by applying Au plating and providing an Au plating layer 302b. However, according to the above conventional manufacturing method. An Au plating layer 2b is formed on the entire surface of the conductor strip 2, and all the conductor strips 2 must be connected to the conductive wiring 3 for electrolytic plating as shown in the plan view of the main part in FIG. Because of the restrictions that cannot be met, there are drawbacks such as the inability to check the continuity of the bonding portion of the semiconductor element. Therefore. The purpose of the present invention was to eliminate the drawbacks of the conventional manufacturing method described above, and to provide corrosion resistance against etching of the conductor strip in the pattern of the conductor strip on the conductor base when forming the conductor strip. The top surface is plated with Au,
This Au plating layer is used as a mass. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a substrate is patterned using a method of manufacturing a semiconductor device.

以下図面を用いて本発明による半導体装置の製造方法に
ついて詳細に説明する。第4図a−gは本発明による半
導体装置の製造方法の一実施例を説明するための要部工
程断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the drawings. FIGS. 4a to 4g are cross-sectional views of essential parts for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention.

まず、同図aにおいて,スプロケツト孔1a..半導体
素子の入る孔1b,1cを形成した絶縁フイルム1上に
Cu等の導体素材となる箔4を貼り付ける。次に同図b
に示すようにこの素材箔4の表面上にフオトレジスト膜
5を塗布し,写真製版によ勺導体細条のパターンを形成
する。次いで同図cに示すように導体素材箔4の表面露
出部分に素材箔4のエツチングに際して耐蝕性を有する
例えばNi,Ag等の金属のメツキ層6を設け、さらに
同図dに示すように導体素材箔4の導体細条をパターニ
ングした面のメツキ層6の上面にのみ電解Auメツキ層
2bを形成する。しかる後、フオトレジスト膜5を除去
し6〔同図e参照〕同図fに示したようにAuメツキ層
2bあ・よびNi,Ag等のメツキ層6をマスクとして
導体素材箔4をエツチングし、同図gに示すように導体
素材箔4の表面2つまね孔1a,1c内の導体素材箔4
の表面に露出しているNi,Ag等のメツキ層6をエツ
チング除去して同図gに示すような導体細条7が形成さ
れる。このような製造方法によれば、Auメツキ層2b
は導体素材箔4の導体細条7の一表面のみに形成される
とともに、この導体細条7のパターンが互いに導通する
ことなく、飼々に隔絶して形成され,さらには導体素材
箔2aとしてCuを用いたことによつてCuとAuとの
層間にNi,Ag等のメツキ層6を有するためCuとA
u間の拡散を阻止する作用を有し6信頼性を大幅に向上
させることができる。
First, in Figure a, sprocket hole 1a. .. A foil 4 made of a conductive material such as Cu is pasted onto the insulating film 1 in which holes 1b and 1c are formed for receiving semiconductor elements. Next, figure b
As shown in FIG. 2, a photoresist film 5 is applied on the surface of this material foil 4, and a pattern of conductor strips is formed by photolithography. Next, as shown in Figure c, a plating layer 6 of a corrosion-resistant metal such as Ni or Ag is provided on the exposed surface portion of the conductor material foil 4 during etching of the material foil 4, and further, as shown in Figure d, a plating layer 6 of a metal such as Ni or Ag is provided. The electrolytic Au plating layer 2b is formed only on the upper surface of the plating layer 6 on the surface of the material foil 4 on which the conductor strips have been patterned. After that, the photoresist film 5 is removed, and the conductor material foil 4 is etched using the Au plating layer 2b and the plating layer 6 of Ni, Ag, etc. as a mask, as shown in FIG. , as shown in FIG.
The plating layer 6 of Ni, Ag, etc. exposed on the surface is etched away to form conductor strips 7 as shown in FIG. According to such a manufacturing method, the Au plating layer 2b
are formed only on one surface of the conductor strips 7 of the conductor material foil 4, and the patterns of the conductor strips 7 are not electrically connected to each other and are formed in a manner that they are separated from each other. By using Cu, there is a plating layer 6 of Ni, Ag, etc. between the layers of Cu and Au.
It has the effect of preventing diffusion between 6 and 6 reliability.

また,上記製造方法によれば、絶縁フイルムの材質、寸
法、形状は,何ら制約を受けるものではなく,また素地
材料6厚み.パター7形状および中間メツキ層の材質、
メツキ厚}よびAuメツキ厚等何ら制限を受けることは
ない。
Further, according to the above manufacturing method, the material, size, and shape of the insulating film are not subject to any restrictions, and the thickness of the base material 6. The shape of the putter 7 and the material of the intermediate plating layer,
There are no restrictions on the thickness of the plating or the thickness of the Au plating.

以上説明したように本発明による半導体装置の製造方法
によれば,導体細条の厚さを自由に厚くすることができ
るため、従来の方法に比較して強度の大きい細条および
幅の細い矩形の細条を自在に形成することが可能となり
、導体細条の導通に対する信頼性を大幅に向上させるこ
とができる極めて優れた効果が得られる。
As explained above, according to the method of manufacturing a semiconductor device according to the present invention, the thickness of the conductor strip can be freely increased, so compared to the conventional method, the thickness of the conductor strip can be increased and the width of the strip can be increased. This makes it possible to freely form conductor strips, resulting in an extremely excellent effect of greatly improving the reliability of conduction of the conductor strips.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はキヤリアテープの一例を示す要部斜視図、第2
図、第3図は従来の製造方法により形成されたキヤリア
テープの一例を示す要部断面図.要部平面図、第4図a
−gは本発明による半導体装置用基板の製造方法の一実
施例を説明するための要部断面工程図である。 1・・・・・・絶縁テープ61a・・・・・・スプロケ
ツト孔、1b,10・・.・・・孔、2・・・・・・導
体細条62a・・・・・・細条素地62b・・・・・・
Auメツキ層.3・・・・・・導電配線.4・・・・・
・導体素地箔. 5・・・・・・ホトレジスト膜、6・
・・・・・メツキ層、7・・・・・・導体細条。
Figure 1 is a perspective view of the main parts showing an example of carrier tape, Figure 2
Figures 3 and 3 are cross-sectional views of essential parts showing an example of a carrier tape formed by a conventional manufacturing method. Main part plan view, Figure 4a
-g is a cross-sectional process diagram of a main part for explaining one embodiment of a method for manufacturing a substrate for a semiconductor device according to the present invention. 1... Insulating tape 61a... Sprocket hole, 1b, 10... ...hole, 2...conductor strip 62a...strip base 62b...
Au plating layer. 3... Conductive wiring. 4...
・Conductor base foil. 5... Photoresist film, 6.
... Plating layer, 7 ... Conductor strips.

Claims (1)

【特許請求の範囲】[Claims] 1 中央部に半導体素子を接続する孔を形成した可撓性
絶縁フィルムと、前記絶縁フィルム上に形成されかつそ
の表面にAuメッキされた導体細条とからなる半導体装
置の製造方法において、前記可撓性絶縁フィルムに導体
細条形成用の素材箔を貼り付ける工程と、前記素材箔上
に耐メッキ、耐腐蝕性を有するレジスト材を塗布して所
定の導体細条パターンを形成する工程と、前記素材箔表
面の細条パターン部分および箔裏面の露出部分に金属層
をメッキする工程と、前記細条パターン部分の金属層上
に金層をメッキする工程と、前記レジスト材を除去する
工程と、前記金属層もしくは金層で被覆されていない部
分の素材箔を蝕孔する工程と、前記金属層の金層で覆わ
れていない部分を腐蝕する工程とから成ることを特徴と
した半導体装置の製造方法。
1. A method for manufacturing a semiconductor device comprising a flexible insulating film having a hole formed in the center for connecting a semiconductor element, and conductive strips formed on the insulating film and having Au plating on the surface thereof. a step of pasting a material foil for forming conductor strips onto a flexible insulating film; a step of applying a plating-resistant and corrosion-resistant resist material onto the material foil to form a predetermined conductor strip pattern; a step of plating a metal layer on the strip pattern portion on the surface of the material foil and an exposed portion on the back side of the foil; a step of plating a gold layer on the metal layer of the strip pattern portion; and a step of removing the resist material. , a semiconductor device comprising the steps of etching a portion of the material foil that is not covered with the metal layer or the gold layer; and corroding the portion of the metal layer that is not covered with the gold layer. Production method.
JP53145914A 1978-11-22 1978-11-22 Manufacturing method of semiconductor device Expired JPS5917978B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53145914A JPS5917978B2 (en) 1978-11-22 1978-11-22 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53145914A JPS5917978B2 (en) 1978-11-22 1978-11-22 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5571033A JPS5571033A (en) 1980-05-28
JPS5917978B2 true JPS5917978B2 (en) 1984-04-24

Family

ID=15395988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53145914A Expired JPS5917978B2 (en) 1978-11-22 1978-11-22 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5917978B2 (en)

Also Published As

Publication number Publication date
JPS5571033A (en) 1980-05-28

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