Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS5917980B2 - Method for manufacturing protrusions on substrate conductor layer - Google Patents
[go: Go Back, main page]

JPS5917980B2 - Method for manufacturing protrusions on substrate conductor layer - Google Patents

Method for manufacturing protrusions on substrate conductor layer

Info

Publication number
JPS5917980B2
JPS5917980B2 JP54025881A JP2588179A JPS5917980B2 JP S5917980 B2 JPS5917980 B2 JP S5917980B2 JP 54025881 A JP54025881 A JP 54025881A JP 2588179 A JP2588179 A JP 2588179A JP S5917980 B2 JPS5917980 B2 JP S5917980B2
Authority
JP
Japan
Prior art keywords
conductor layer
electronic component
photoresist
substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54025881A
Other languages
Japanese (ja)
Other versions
JPS55118642A (en
Inventor
千善 埴原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suwa Seikosha KK
Original Assignee
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suwa Seikosha KK filed Critical Suwa Seikosha KK
Priority to JP54025881A priority Critical patent/JPS5917980B2/en
Publication of JPS55118642A publication Critical patent/JPS55118642A/en
Publication of JPS5917980B2 publication Critical patent/JPS5917980B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、半導体素子などの電子部品素子の電極と外部
基板との電気的接続を得るために使用する基板への電気
的接続用突起の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a protrusion for electrical connection to a substrate, which is used to obtain an electrical connection between an electrode of an electronic component element such as a semiconductor device and an external substrate.

従来、半導体素子などの電子部品素子の電極と外部基板
との電気的接続の方法としてぱ、第1図に示す如く、半
導体素子1上に、写真食刻技術を用いて、所望のパター
ン構造にAt電極2が形成され、このAt電極2と、外
部基板と電気的接続をする部分をのぞく、半導体素子1
の全面には、: 素子表面を保護するためにSiO2の
絶縁膜3が写真食刻技術により形成され、絶縁膜3の形
成されていない外部基板との電気的接続部には、Cu、
Au、半田等の一種あるいは二種からなる金属層がメッ
キにより被着形成されておV、これにより0 バンプ4
を構成し、外部基板との電気的接続をとるようになつて
いる。しかし、このような工程においては、電子部品素
子の製造に多くの工数を必要とし、又、歩留りも悪く、
メッキ処理が原因となる電子部品素子自体の電気的特性
に及ぼす悪影5 響があつた。本発明はかかる欠点を除
去するためになされたものである。本発明の一実施例を
第5図a、bに示すような。
Conventionally, as a method for electrically connecting an electrode of an electronic component element such as a semiconductor element to an external substrate, as shown in FIG. A semiconductor element 1 except for a portion where an At electrode 2 is formed and electrically connected to the At electrode 2 and an external substrate.
An insulating film 3 of SiO2 is formed on the entire surface of the device by photolithography to protect the element surface, and electrical connections with an external substrate on which the insulating film 3 is not formed are coated with Cu,
A metal layer consisting of one or two types of Au, solder, etc. is deposited and formed by plating, thereby forming a 0 bump 4.
It is configured to make an electrical connection with an external board. However, in such a process, many man-hours are required to manufacture electronic components, and the yield is also low.
The plating process had an adverse effect on the electrical characteristics of the electronic component itself. The present invention has been made to eliminate such drawbacks. An embodiment of the present invention is shown in FIGS. 5a and 5b.

時計用のテープキャリア基板への応用を例に第2図につ
いて説明すると、1は導体層表面にフォトiOレジスト
を塗布する第1の工程である。5がフォトレジスト、6
が銅等の金属箔からなる導体層。
To explain FIG. 2 using an example of application to a tape carrier substrate for a watch, 1 is a first step of applying a photo-iO resist on the surface of a conductor layer. 5 is photoresist, 6
is a conductor layer made of metal foil such as copper.

1がたとえばフレキシブルなポリイミドフィルムのよう
な絶縁層である。
1 is an insulating layer such as a flexible polyimide film.

フォトレジスト5は、数ミクロンの厚さで均一に塗布し
なければならない■5 ため、第3図に示すような特殊
のロールコーターにより塗布している。コーター用ロー
ラー13によりかき上げられてきたフォトレジスト15
を。押し付け用ローラー14との間にはさまれたテープ
キャリア16に塗布する。2は導体層6裏面に30写真
食刻をする第2の工程である。
Since the photoresist 5 must be uniformly coated to a thickness of several microns, it is coated using a special roll coater as shown in FIG. Photoresist 15 scraped up by coater roller 13
of. It is applied to the tape carrier 16 sandwiched between the pressing roller 14 and the tape carrier 16 . 2 is a second step in which 30 photo-etchings are made on the back surface of the conductor layer 6.

8は写真食刻によシ作られた突起である。8 is a protrusion made by photoetching.

導体層6裏面の場合は、絶縁層Tの厚み分クリアランス
ができるためフォトレジスト51の塗布がむずかしいが
、第1の工程1で説明したロールコーターのローラー回
35転数、ローラー押付圧等の条件を適正値にセットし
塗布している。露光は、部品精度がでるよう1/2プロ
ジェクション露光法を行なつている。次に現像を数分お
こない,フオトレジストによるパターンを形成し、後に
適当な食刻液に数分浸漬し、導体層の半分程度を食刻す
る。3は導体層6表面のパターニングをする第3の工程
である。
In the case of the back side of the conductor layer 6, it is difficult to apply the photoresist 51 because there is a clearance equal to the thickness of the insulating layer T, but the conditions such as the number of rotations of the roll coater (35 rotations) and the roller pressing pressure as explained in the first step 1. is set to an appropriate value and applied. For exposure, a 1/2 projection exposure method is used to ensure component accuracy. Next, development is performed for several minutes to form a photoresist pattern, and then about half of the conductor layer is etched by immersing it in a suitable etching solution for several minutes. 3 is a third step of patterning the surface of the conductor layer 6.

導体層6裏面突起部との位置を出し,導体層6表面に1
/2プロジエクシヨン露光法により露光し6現像を数分
行い、フオトレジストによるパターン9を形成する。4
は.5において導体層表面の食刻をする時、導体層6裏
面が食刻されない保護のためのコーテイング剤の塗布を
する第4の工程である。
The position of the protrusion on the back surface of the conductor layer 6 is determined, and the
Exposure is performed using a /2 projection exposure method, and development is performed for several minutes to form a pattern 9 of photoresist. 4
teeth. The fourth step is to apply a coating agent to protect the back surface of the conductor layer 6 from being etched when the surface of the conductor layer 6 is etched in step 5.

10がコーテイング剤である。10 is a coating agent.

5は導体層6表面からの食刻をする第5の工程である。5 is a fifth step of etching the surface of the conductor layer 6.

11は食刻されてなくなつた部分、12は食刻によ如形
成された電気的接続用突起のついた接続用端子である。
Reference numeral 11 indicates a portion that has been etched away, and reference numeral 12 indicates a connection terminal having an electrical connection protrusion formed by etching.

6B1,2,4工程で塗布されたフオトレジスト及び導
体層6裏面のコーテイング剤の剥離をする第6の工程で
ある。
6B This is a sixth step in which the photoresist applied in steps 1, 2, and 4 and the coating agent on the back surface of the conductor layer 6 are removed.

以上の工程により作られた電気的接続用突起のついた接
続用端子の形成されたテープキヤリアに図示しないAu
メツキ等の所望工程を経て第4図に示す如く、半導体素
子との間で位置出しをし6熱圧着をすれば、半導体素子
と外部基板との電気的接続ができる。
Au (not shown) is attached to the tape carrier on which connection terminals with electrical connection protrusions are formed by the above process.
After performing a desired process such as plating, as shown in FIG. 4, the semiconductor element is positioned with respect to the semiconductor element and thermocompression bonding is performed (6) to establish electrical connection between the semiconductor element and the external substrate.

このような工程によシテープキヤリアへ電気的接続用突
起を設ければ、半導体素子側へバンプ4を作る必要がな
くなる。
By providing electrical connection protrusions on the tape carrier through such a process, it is no longer necessary to form bumps 4 on the semiconductor element side.

以上の説明においては.フオトレジストの塗布にロール
コーターを使用すると説明したが,スピンナー,スクリ
ーン印刷,タコ印刷、適下させてスキージする方法等を
用いてもよく上記の方法に限定されるものではない。
In the above explanation. Although it has been explained that a roll coater is used to apply the photoresist, a spinner, screen printing, tacho printing, dropping method and squeegee method, etc. may be used, but the method is not limited to the above method.

又.電子部品素子として,半導体素子について説明した
が、抵抗、コンデンサ等に応用することもできる。以上
の如く6本発明によれば、電子部品素子の電極と外部基
板との電気的接続を行なう基板の導体層上であつて6し
かも電子部品素子の電極と接続される部分に突起を設け
ることによV)6従来の電子部品素子の電極上に形成し
ていたバンプが不要とな抵このバンプ形成の為のメツキ
処理の必要もなくなるため.メツキ処理による悪影響が
なくなり電子部品素子自体の信頼性が向上し6又電子部
品製造の工数が削減され、歩留りも向上する。
or. Although a semiconductor element has been described as an electronic component element, it can also be applied to resistors, capacitors, etc. As described above, according to the present invention, protrusions are provided on the conductive layer of the substrate that makes electrical connection between the electrodes of the electronic component element and the external substrate, and in the portion that is connected to the electrode of the electronic component element. V) 6 The bumps that were formed on the electrodes of conventional electronic component elements are no longer required.There is no need for plating processing to form resistor bumps. The adverse effects of the plating process are eliminated, the reliability of the electronic component element itself is improved, the number of man-hours for manufacturing the six-pronged electronic component is reduced, and the yield is also improved.

周.本発明により、従来の基板製造工程に6本発明の第
2の工程が付加されるが、工数負荷も少なくバンプ不用
とした方が効果大である。
Zhou. According to the present invention, six second steps of the present invention are added to the conventional board manufacturing process, but it is more effective to reduce the man-hour load and eliminate the need for bumps.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体素子を説明するための要部断面図
、第2図は,本発明によるテープキヤリアへの電気的接
続用突起製造方法の一実施例の工程別要部断面図。 第3図は,本発明で使用したロールコーターの要部断面
図,第4図は6本発明により製造された電気的接続用突
起を有するテープキヤリアと半導体素子の圧着状態を示
す要部断面図。第5図A,bは、本発明の一実施例とし
て時計用のテープキヤリア基板の一部を示す説明図であ
り.aは表面、bは裏面である。1・・・半導体素子,
2・・・At電極.3・・・絶縁膜、4・・・バンプ,
5・・・フオトレジスト、6・・・導体層67・・・
絶縁層.8・・・突起. 9・・・フオトレジストによ
るパターン、10・・・コーデイング剤.12・・・接
続用端子。
FIG. 1 is a cross-sectional view of a main part for explaining a conventional semiconductor element, and FIG. 2 is a cross-sectional view of a main part by step of an embodiment of the method of manufacturing a protrusion for electrical connection to a tape carrier according to the present invention. FIG. 3 is a cross-sectional view of a main part of the roll coater used in the present invention, and FIG. . FIGS. 5A and 5B are explanatory diagrams showing a part of a tape carrier board for a watch as an embodiment of the present invention. a is the front surface and b is the back surface. 1... semiconductor element,
2...At electrode. 3... Insulating film, 4... Bump,
5... Photoresist, 6... Conductor layer 67...
Insulating layer. 8... Protrusion. 9... Pattern by photoresist, 10... Coding agent. 12... Connection terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 電子部品素子の入る開孔部を有する樹脂材で構成さ
れた絶縁層と、前記開孔部を覆うように前記絶縁層上に
被覆された銅等の金属箔からなる導体層とを具備して電
子部品素子と外部基板との電気的接続を行なう基板にお
いて、前記導体層の前記電子部品素子の電極と接続され
る部分への突起製造方法として、前記導体層の表面にフ
ォトレジストを塗布する第1の工程と前記導体層の裏面
にフォトレジスト塗布・露光・現像・食刻からなる写真
食刻をする第2の工程と、前記導体層の表面に露光・現
像からなるパターニングをする第3の工程と前記導体層
の裏面にコーティング剤を塗布する第4の工程と前記導
体層の表面の食刻をする第5の工程と、前記導体層の表
及び裏面のフォトワジスト及びコーティング剤を剥離す
る第6の工程を有することを特徴とする基板導体層への
突起製造方法。
1. An insulating layer made of a resin material having an opening into which an electronic component element can be inserted, and a conductor layer made of a metal foil such as copper coated on the insulating layer so as to cover the opening. In a substrate for electrically connecting an electronic component element and an external substrate, a method for manufacturing a protrusion on a portion of the conductor layer to be connected to an electrode of the electronic component element includes coating a surface of the conductor layer with a photoresist. a first step; a second step of photo-etching the back surface of the conductor layer, which consists of photoresist coating, exposure, development, and etching; and a third step, which involves patterning the surface of the conductor layer, which consists of exposure and development. a fourth step of applying a coating agent to the back surface of the conductor layer; a fifth step of etching the surface of the conductor layer; and peeling off the photowaste and coating agent on the front and back surfaces of the conductor layer. A method for manufacturing protrusions on a substrate conductor layer, comprising a sixth step.
JP54025881A 1979-03-06 1979-03-06 Method for manufacturing protrusions on substrate conductor layer Expired JPS5917980B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54025881A JPS5917980B2 (en) 1979-03-06 1979-03-06 Method for manufacturing protrusions on substrate conductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54025881A JPS5917980B2 (en) 1979-03-06 1979-03-06 Method for manufacturing protrusions on substrate conductor layer

Publications (2)

Publication Number Publication Date
JPS55118642A JPS55118642A (en) 1980-09-11
JPS5917980B2 true JPS5917980B2 (en) 1984-04-24

Family

ID=12178117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54025881A Expired JPS5917980B2 (en) 1979-03-06 1979-03-06 Method for manufacturing protrusions on substrate conductor layer

Country Status (1)

Country Link
JP (1) JPS5917980B2 (en)

Also Published As

Publication number Publication date
JPS55118642A (en) 1980-09-11

Similar Documents

Publication Publication Date Title
US4466181A (en) Method for mounting conjoined devices
US6617236B2 (en) Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device
US6472609B2 (en) Printed-wiring substrate and method for fabricating the printed-wiring substrate
JP3178417B2 (en) Semiconductor carrier and method of manufacturing the same
JP3263875B2 (en) Method for manufacturing surface-mounted electronic component and surface-mounted electronic component
JPS5917980B2 (en) Method for manufacturing protrusions on substrate conductor layer
JPH02280334A (en) Semiconductor device and manufacture thereof
JP2752852B2 (en) Method for manufacturing TAB tape carrier
JP2727870B2 (en) Film carrier tape and method of manufacturing the same
JP2000309151A (en) Printing method for pasty substances
JP2661280B2 (en) Tape carrier structure
JP3019556B2 (en) Lead frame manufacturing method and semiconductor device manufacturing method
JPS628945B2 (en)
KR0186208B1 (en) Bump structure
JPH0795556B2 (en) Tape carrier manufacturing method
JP2795475B2 (en) Printed wiring board and manufacturing method thereof
JPH05226385A (en) Packaging of semiconductor device
JP2827393B2 (en) Method for forming conductive protrusions on lead portion of TAB tape
JP2849870B2 (en) Method of forming bump on electronic component mounting substrate
JP3226010B2 (en) Method of manufacturing film carrier for semiconductor device
JPH0382095A (en) Connection of semiconductor ic
JPH0354873B2 (en)
JPS6334937A (en) Manufacture of film carrier
JPS5819152B2 (en) Insatsu High Senkiban no Seizouhouhou
JPH04219935A (en) Manufacture of connection terminal