JPS59183B2 - Synchronization method - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a synchronization method in a secret communication device that provides secrecy by dividing input signals into units of time and changing the arrangement on the time axis for each unit of time. .

FIG. 1 is a block wiring diagram 9 showing an example of a conventional secret device synchronization system. In the figure, 1 is a signal input terminal, 2 is a transmitting A/D converter that digitizes this input signal, and 3 is this transmitting A/D converter. 4 is a transmission memory circuit 3 for dividing the output of the /D converter 2 into units of time and temporarily storing the output.
5 is a synchronous signal generator that is controlled by this transmission control circuit 4 and generates time information for each storage unit time of the transmission memory circuit 3; 6 is this synchronous signal generator. T is a transmission D/A converter that converts the confidential digital signal from the memory circuit 3 into an analog signal, and 8 is this transmission D/A converter. 7 is a transmission secret signal filter that limits the band of the converted analog signal; 9 is a synthesis circuit that synthesizes the secret signal 8 from this transmission secret signal filter and the synchronization signal from the transmission synchronization signal filter 6; 10 is this synthesis circuit. 11 is a receiving amplifier that receives and amplifies the signal sent through this transmission line 10; 12 is a receiving amplifier that passes only the synchronizing signal component of the output of this receiving amplifier 11; A reception synchronization signal filter, 13 a synchronization signal detector that detects a synchronization signal from the output of this filter, 14 a reception secret signal filter that passes only the secret signal component from the output of the reception amplifier 11, and 15 a secret signal that is the output of this filter. A reception A/D converter 16 converts the digital signal into a digital signal, a reception memory circuit 16 stores this digital signal, and an IT rearranges this stored signal with the synchronization signal from the synchronization signal detector 13. a reception control circuit that performs control to restore the secret signal to the original signal, 18 a reception D/A converter that converts this rearranged digital signal into an analog signal; 19
is the output terminal.

In the secret device synchronization method configured as above,
Based on the control signal from the transmission control circuit 4, the signals stored in the transmission memory circuit 3 are divided into units of time and are read out in the same direction or in the opposite direction as when they were stored, with a predetermined length as one unit. The signals are arranged in a different arrangement from the input signal to create a secret signal.

At this time, a synchronization signal is synthesized by a synthesis circuit 9 and sent out as a reference for restoring the confidential signal to the original signal on the receiving side.
Methods for transmitting this synchronization signal include a frequency division method in which it is transmitted as a continuous wave signal and a time division method in which it is transmitted as an intermittent signal.

FIG. 2 is a distribution diagram of the spectrum of the frequency-divided secret signal and synchronization signal. The secret signal has a spectrum from f1 to F, but the transmission synchronization filter 6 divides the band into
In order to synthesize the synchronization signal limited to , the transmission privacy filter 8 limits the band to f1 to F2 and f3 to F4.

That is, in order to send a synchronization signal, the information between F2 and F3 of the confidential signal is truncated. FIG. 3 is a diagram showing the time course of the secret signal level and the synchronization signal level in the time division system. The synchronization signal is transmitted for △t time every T1 time, and the transmission of the secret signal is stopped during this Δt time. be done.

In this case, the transmission synchronization filter 6, the transmission secret signal filter 8, the reception synchronization signal filter 12, and the reception secret signal filter 14 are unnecessary, but the secret signal loses information for a minute time Δt.

As mentioned above, in the frequency division method of the U.S.-based synchronization method, the disadvantage is that in order to stably transmit and receive synchronization signals within the band, the transmitting and receiving synchronization signal filters and the transmitting and receiving secret signal filters must be large and sophisticated. It was hot. In addition, the time division method has the disadvantage that in order to stably transmit and receive the synchronization signal, the transmission time of the synchronization signal must be increased, which impairs the quality of the secret signal. The object of the present invention is to obtain a stable synchronization method that does not impair the quality of the confidential signal without using a large and high-grade filter.

Since the synchronization method of this invention uses a time division method, an example of the block connection diagram is shown in FIG.
Reception synchronization signal filter 12 and reception secret signal filter 1
It is exactly the same as the one with 4 deleted.

FIG. 4 is an explanatory diagram of the operation of the synchronization system of the present invention. FIG. 4a shows the temporal change in the storage of the input signal in the transmission memory circuit. The input signal is divided into multiple units per unit time t1 (the figure shows the case where m=5) T1...T
5 is stored in the memory circuit. That time T8 is Mtl
(5t1 in the figure). FIG. 4b shows the secret signal m+1 read out from the memory circuit.

Since the reading speed is 1 m times the writing speed (in the figure, m-5, that is, the second time), the unit time T2 for reading m is T2?
It becomes t1.

m and a half 1 However, Ts'''Mtl Therefore, T8=(m+1)T2 During time T8, the synchronizing signal S can be added next to m units (Ti...Tmf) (5 units in the figure).

In this case, Ti...Tm are read out and arranged in the same direction or in opposite directions in order to give a secret characteristic to T1...T5. FIG. 5 is a spectrum distribution diagram of one unit of the input signal and the secret signal.

In the figure, A shows the spectrum of the input signal, and B shows the spectrum of the secret signal. In this case, B has a wider band than A, and the following relationship exists between its highest spare drum frequencies f1 and F2. In order to transmit the input signal and the secret speech signal in the same band, it is necessary to remove the frequency components higher than f1 of the secret speech signal (part c in Figure 5), but the high frequency part of the voice contains less information. Yes 5th
Even if part c in the figure is deleted, the loss of information can be said to be extremely small.

To restore the original signal on the receiving side, the operation on the transmitting side is reversed. As described above, the present invention has the advantage that extremely stable synchronization can be achieved with an extremely simple configuration in which the writing speed and reading speed of the memory circuit are changed.

[Brief explanation of the drawing]

Figure 1 is a block wiring diagram showing an example of the synchronization method of Jumei's secret device, Figure 2 is a spectrum distribution diagram of Jumei's frequency division method, and Figure 3 is the secret signal level and synchronization signal level of Jumei's time division method. FIG. 4 is an explanatory diagram of the operation of the synchronization system of the present invention, and FIG. 5 is a spectrum distribution diagram of the confidential signal of the present invention. In the figure, 1 is a signal input terminal, 3 is a transmission memory circuit, and 4 is a signal input terminal.
is a transmission control circuit, 5 is a synchronization signal generator, 9 is a synthesis circuit,
11 is a reception amplifier, 13 is a synchronization signal detector, 16 is a reception memory circuit, 17 is a reception control circuit, and 19 is an output terminal.

Claims (1)

[Claims] 1. A memory circuit that divides and stores input signals in units of time, reads out the memory contents of this memory circuit for each unit of time in the same direction or in the opposite direction to the time of storage, and performs cooling distribution that is different from the input signal for each unit of time. A synchronization system characterized in that the memory contents stored in the memory circuit are read out at a speed (m+1)/m times the memory write speed, and a synchronization signal of one unit time is added every m units.