JPH0669176B2 - Secret communication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit for maintaining confidentiality (privacy) of a call in wired or wireless communication. More specifically, the communication will be described above. The present invention relates to a signal synchronization system of a system.

(B) Conventional technology In wired or wireless communication, if a proper receiving device is used, the content of communication is intercepted by anyone, and the confidentiality of the call is impaired. As a method to solve this problem, scramble the audio signal and send it out,
Even if it is received by a third party, the content is not understood as it is, and only the receiver having a circuit (descramble processing circuit) for reproducing this processed signal can restore the audio signal, a so-called scramble technology. Has been used conventionally. Examples of conventional confidential communication systems include, for example, the Institute of Electronics and Communication Engineers (August 1982) “secret communication technology” and “P832”.
~ P834) and IEICE Technical Report CS80-149 (1980 11
Monthly) Various methods are introduced in "About confidential methods". Since the voice information is composed of the spectrum and its change with time, the intelligibility of the voice can be lowered by the scrambling process for changing the spectrum structure. From this point of view, as a scramble system that has been put into practical use so far, there is a frequency division replacement method of a spectrum inversion method. For example, Japanese Patent Publication Sho 58-8621 (H0
4K1 / 04) "Unspoken method with frequency correction function" and Japanese Patent Laid-Open No. 5
8-148541 (H04K1 / 04) "Secret circuit" relates to the spectrum reversal secret method, and Japanese Patent Publication Sho 58-24984 (H04K1 / 06)
"Secret device" relates to a method of performing signal processing after dividing into a predetermined spectrum, and the technical report of the Institute of Electronics and Communication Engineers CS-80-14.
9 proposes a method for improving the frequency axis conversion processing by FFT processing after converting the audio signal into a digital signal. Therefore, the spectrum inversion method cannot take a sufficient number of combinations (keys) for the secret story. Also, in the latter two methods, there are problems that the number of keys is large, but many filters are used and an FFT processing circuit is required, the circuit scale becomes large, the cost is high, and the power consumption is large.

From these points of view, as a scramble system with a large number of keys, excellent secret story performance, and a simple circuit configuration,
The applicant of the present invention has previously disclosed Japanese Patent Application Laid-Open No. 59-52941 (Japanese Patent Application No. 57-164763), Japanese Patent Application Laid-Open No. 59-72837 (Japanese Patent Application No. 57-184916), Japanese Patent Application Laid-Open No. 60-89143 ( Japanese Patent Application No. 58-197021).

This is a technique in which a variable delay circuit such as a BBD is used to periodically change the frequency of a clock for controlling the delay time and to repeatedly compress and expand the time axis.

That is, the transmitting side scrambles the audio signal and sends it out.

Then, on the receiving side, signal processing reverse to that on the transmitting side is performed in order to correctly restore the original voice.

However, for this purpose, it is necessary to synchronize the operation of the clock applied to the variable delay circuit on the transmitting side and the receiving side.

Therefore, the sync signal may be multiplexed with the scrambled voice.

There are a frequency multiplexing method and a time axis multiplexing method for multiplexing this signal.

The present application provides a time-base multiplex system confidential communication method that can be synchronized on the transmitting and receiving sides without expanding the transmission band.

For time-axis multiplexing, usually, as shown in Japanese Patent Laid-Open No. 54-151312, a memory circuit is used to compress a signal to provide a time gap, and a synchronization signal is multiplexed in the gap portion. To send.

(C) Problems to be Solved by the Invention The present invention provides a confidential communication method in which the memory for the time base compression is also used as the memory for the scramble only.

(D) Means for Solving the Problems In the present invention, a memory element such as a RAM is used as a variable delay circuit to periodically change the frequency of a write / read clock to scramble an audio signal and at the same time to generate a sync signal. Is transmitted by time division multiplexing.

That is, the frequency of the privacy communication method of the present invention, write an audio signal in the storage means (3) by a write clock (f ₁₎ whose frequency varies periodically, the frequency change is the write clock (f ₁₎ Of the write clock (f ₁ ) and the number of clocks in one cycle (t1-t5, t5-t9) of the write clock (f ₁ ) is less than one cycle (t2-t4, t6-t8). With the read clock (f ₂ ) output by, the audio signal written approximately half cycle before is read out, so that the read audio signal has a time gap (1) for inserting a synchronization signal for each cycle of the write clock. t4-t6, t8-t10) are provided, and the synchronizing signal is multiplexed in this time gap (t4-t6, t8-t10).

(E) Action In the present invention, the change in the frequency of the write clock and the change in the frequency of the read clock are almost the same phase, but the write and read timings are shifted by a half cycle. The clock frequency is read out early to compress and expand the audio signal.

Further, the synchronization signal is inserted into this write / read clock every cycle.

(F) Example The structure of the present invention is shown in FIG. 1 and FIG. First, the structure of the transmitting side will be described with reference to FIG. (1) is a sample and hold circuit for audio signals, (2) is an A-D conversion circuit,
(3) is a storage means such as RAM, (4) is a D-A conversion circuit,
(5) is an LPF, and (6) is a clock frequency control circuit, which is composed of a microcomputer or the like. (7) is a synchronization signal generation circuit,
(8) is an adder circuit for the synchronization signal and the scramble signal,
(9) is a transmission circuit. The sample hold circuit (1), the storage means (3), and the synchronizing signal generating circuit (7) are controlled by the clock frequency control circuit (6).

Next, the configuration of the receiving side will be described with reference to FIG.

(10) is the receiving circuit, (11) is the sample and hold circuit,
(12) is an A-D conversion circuit, (13) is storage means such as RAM,
(14) is a D-A conversion circuit, (15) is an LPF, (16) is a clock frequency control circuit, and (17) is a synchronization signal discrimination circuit. A synchronization signal discrimination circuit (17) extracts a synchronization signal from the received signal and initializes the clock frequency control circuit (16).

Next, the operation when RAM is used as the storage means will be described. A clock frequency f ₁ (t) when the signal is sampled by the output of the clock frequency control circuit (6) on the transmission side and written to the RAM (3) and a clock frequency f ₂ (t) when read from the RAM (3) The scrambling process is carried out by changing the value of RA, and on the other hand, on the receiving side, the clock frequency control circuit (16) reverses RA at the clock frequency f ₂ (t).
The signal is restored by writing to M (13) and reading at the clock frequency f ₁ (t). f ₁ (t) and f
₂ (t) is changed with a cycle of the sum of the delay times in the RAMs (3) and (13) on the transmission / reception side. Where f ₁ (t) and f ₂
Consider a case where (t) is changed as shown in FIG.
f ₁ (t) and f ₂ (t) are respectively f _{1L to} f with time.
_1H , f _{2L to} f _2H are changed in a triangular wave shape with a period of time (tf). However, the time _{t 1 ~t 2, t 4 ~t} 6, t 8 ~t 10 is for use as a synchronization signal section to be described later, f ₂ (t) shall not be statement. The data taken in the storage means (3) between the time (t ₁ ) and the time (t ₃ ) at the clock frequency f ₁ (t) is the data (t ₄ ) after the time (t ₃ ) at the clock frequency f ₂ (t). ), The data is read from the storage means (3). That is, f ₁ (t) and f ₂ (t) satisfy the following relationship.

And the number of clocks f ₁ between time t ₁ ~t ₃ (t), the time _{(t 3) ~ (t 4} ) the number of clocks f ₂ (t) between the same.

(However, f ₁ (t) and f ₂ (t) indicate the clock frequency at time (t).) Also, at the clock frequency f ₁ (t), from time (t ₃ ) to (t ₅ ).
The data taken into the storage means (3) during the period is read from the storage means (3) between the time (t ₆ ) and the time (t ₇ ) at the clock frequency f ₂ (t). Then, the synchronization signal is superimposed in the section from time (t ₄ ) to (t ₆ ). On the receiving side, conversely, at the clock frequency f ₂ (t), the time (t ₃ ) to (t ₄ ) and (t ₆ )
The data taken into the RAM (13) during the period (t ₇ ) to (t ₇ ) is the time between the time (t ₅ ) and (t ₉ ) at the clock frequency f ₁ (t).
3) is read from and restored to the original signal. On this occasion,
The sync signal section is ignored.

Synchronization signal synchronizing signal generating circuit (7) from the synchronizing signal section (t ₄ ~t _6), and output signals of a predetermined waveform (t ₈ ~t ₁₀₎ (e.g., a sine wave, etc.). This control is performed by the clock frequency control circuit (6). On the receiving side, the synchronizing signal discriminating circuit (17) extracts the synchronizing signal, detects the timings (t ₂ ) and (t ₆ ) of the clock frequency change, and generates a pulse (FIG. 4). Clocks are synchronized on the transmitting and receiving sides by initializing the receiving side clock frequency control circuit (16) with a pulse from the synchronizing signal discrimination circuit (17). By changing the cycle (tf) and phase of the clock frequency change, it is possible to increase the number of key combinations (secret keys).

(G) Effect of the Invention As described above, in the present invention, the frequency change cycle of the write clock on the transmission side and the frequency change cycle of the read clock are
Since they are the same and their phases are almost the same, it is easy to create the frequencies of these two types of clocks.

Moreover, in the present application, since the audio signal written almost half cycle before is read by the read clock (f ₂ ), the audio signal can be compressed and expanded more efficiently.

As described above, according to the present application, the cycle of frequency change of the write / read clock and the cycle of synchronization signal can be made substantially the same, and even if the phases of frequency change of the write clock and the read clock are set to be substantially the same. , Scrambling can be performed well.

[Brief description of drawings]

FIG. 1 and FIG. 2 are configuration diagrams of a transmission side and a reception side of a confidential communication device which is the basis of the present invention, FIG. 3 is an explanatory diagram of a clock frequency change, and FIG. 4 is an explanatory diagram of a synchronization signal. . (1) (11) …… Sample and hold circuit, (2) (12)
... A / D conversion circuit, (3) (13) ... storage means,
(4) (14) …… D / A conversion circuit, (5) (15) …… LP
F, (6) (16) …… Clock frequency control circuit, (7)
…… Synchronization signal generation circuit, (17) …… Synchronization signal discrimination circuit.

Continuation of front page (56) References JP 59-52941 (JP, A) JP 60-89143 (JP, A) JP 54-151312 (JP, A)

Claims (1)

[Claims] _{1. A} voice signal is written to a storage means (3) by a write clock (f ₁ ) whose frequency changes periodically, and the change in frequency is almost the same as the change in frequency of the write clock (f ₁ ). read clock generated by the phase, and, for outputting in the write clock clock number of periods of less than one period of one period (t1-t5, t5-t9 ) of _{(f 1) (t2-t4} , t6-t8) At (f ₂ ), the audio signal written approximately half a period before is read out, so that a time gap (t4−t6, t8) for inserting a synchronization signal into the read audio signal is obtained every one cycle of the write clock. -T10) is provided, and the synchronization signal is multiplexed in this time gap (t4-t6, t8-t10).