JPS5918749B2 - Pseudo error sending method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pseudo column storage device using an IC memory for easily simulating the operation when a storage medium is defective in a magnetic disk device, etc. The present invention relates to a system that includes an error data register and sends a pseudo error in place of IC memory read data.

If there is a defect in the storage medium in a magnetic disk device used as an external storage device for a computer system, the channel device and magnetic disk control device connected to the computer's central processing unit will operate according to the nature of the defect. It is prescribed to do so.

Conventionally, testing of channel devices, etc. regarding the content of defects has been done by physically attaching a Π to the medium itself, but this method has a limitation on the content of defects that can occur, and also causes the medium itself to become defective. Therefore, it is expensive, and the method being tried involves writing data corresponding to the defect content each time into an IC memory that simulates a media defect, and then reading it out, so that it is possible to eliminate a large number of defect contents in a short period of time. It was something that was difficult to imitate internally. An object of the present invention is to provide an efficient method for generating defects in a pseudo external storage device that simulates a magnetic storage medium.

According to the present invention, an IC memory is used in place of a magnetic storage medium such as a magnetic disk device connected to a channel device, and an address counter that counts clock signals as a medium address is used to receive address instructions from the channel device. In a pseudo external storage device that reads and writes to IC memory based on a match with an address counter, an error/data register for storing error/data and an error/address register for specifying an error/address are provided, and an error/address register for indicating an error address is provided.・Writes error information to the address register and detects the error by the read signal from the channel device. ・Replaces the error with IC memory read data at the matching contact between the address register and the address counter. ・Data register A pseudo-error sending method for sending the contents of is obtained.

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a system block diagram showing the configuration of an embodiment of the present invention. The disk controller DPC controls the channel device CHC based on the instructions from the central processing unit CPU of the computer system.
The controller receives the disk unit number, track instruction, and operation mode sent through the disk unit, selects the specified disk unit, in this case the pseudo disk device 1, and specifies the track. The pseudo disk device 1 is composed of an IC memory 3 that takes the place of a magnetic storage medium, and a pseudo disk unit 2 that pseudo-controls the C memory 3 as a disk unit. Furthermore, the pseudo disk device 1 is a computer
It is connected to the central processing unit CPU via a service processor SVPl that monitors the system and signal lines T2 and t3. The service processor SVP communicates with the channel device ℃HC and the magnetic disk controller DPC through the signal transmission T2.
The central processing unit CPU is connected to the channel device CH.
It is possible to monitor the response to the test program executed on the Cl magnetic disk controller DPC. FIG. 2 is a block diagram of a pseudo disk device showing one embodiment of the present invention.

The same parts as in FIG. 1 are given the same reference numerals. The pseudo disk device 1 includes a C memory 3 that takes the place of a magnetic storage medium;
The control unit 4 that connects and controls the C memory 3 to the magnetic disk controller DPC reads out data read from the IC memory 3. an error data register R2 that stores the error contents transferred from the service processor SVP, an error address register R3, R3'', and an address counter ACl that counts continuous clock signals.
The address counter AC provides a byte address on a virtual track to the 1C memory 3, which is a random access memory.

Error data register R2 stores one byte of error data that causes an error, error address register R3 stores the address on the track that causes the error, and R3'' stores that track. In the figure: During data writing, write data sent bit serially through the signal line t1 is collected in byte units by the control unit 4 and sent to the IC memory 3 through the signal line T4.The address input of the IC memory 3 is track designation information. is given from the control unit 4 via the signal line T5, and the address on the track is given from the address counter AC via the signal line T6.The control unit 4 receives the track received from the channel device CHC and stores it. By detecting a match between the local byte address and the address counter AC, the write data can be written to the IC memory 3 from the timing of the match. When reading data, the IC memory 3 is read in byte units from the coincidence timing of the byte address stored in the control unit 4 and the address counter AC, and the data register R1 and the control unit 4
, is sent bit serially via the signal line t1 〇In this way, when reading and writing to the IC memory 3, the function of the address counter AC simulates writing and reading to a magnetic disk. I can do it.

By the way, a method for simulating a case in which data cannot be written or read satisfactorily due to the surface of the storage medium of a magnetic disk, such as scratches or scratches, is carried out as follows. Assuming that correct data has already been written to the pseudo disk device 1 according to the method, the intermediate processing unit CPU sends the error occurrence address and error data via the signal line T2 by the service processor SVP. - Transfer to address registers R3, R3' and error data register R2.Then, the central processing unit CPU gives a read command, and the pseudo disk device 1 transfers the bytes stored in the address counter AC and the control unit 4 as described above. IC memory 3 from address match timing
Read and start data transmission. Address comparison circuit CM
, the address stored in the error address register R3 is compared with the address of the address counter AC, and the matching timing is known, and the error data register R is stored.
The error data of No. 2 is converted into the read output of the C memory 3 and sent from the control section 4 through the signal line t1. after this,
When the contents of the 1C memory 3 indicated by the address counter AC are read out and the record break is identified, the read operation ends. Here, when the control unit 4 receives a retry read instruction, it does not send the output of the error data register R2, but sends the read output of the IC memory 3, making it possible to easily confirm the success of the retry. It is.

FIG. 3 is a flow diagram showing the process of sending error data from the pseudo disk device.

In step 10, the central processing unit CPU sets error contents in the error data register R2 and error address registers R3 and R3l by the service processor SVP in order to simulate a read/write error in the storage medium. Next, in step 11, the pseudo disk device 1
receives the read instruction and sends the contents of the error data register R2 to the central processing unit CPU at the timing when the address counter AC and the error address counter R3 match, as shown in step 15. If the addresses do not match, read the contents of the IC memory 3 and proceed to step 14.
When a record break is identified at , the read operation ends. As explained in the above embodiment, when reading in a pseudo disk device that simulates a magnetic disk, error contents are set arbitrarily from the male part that does not go through the channel device, and the occurrence of an error is simulated. Compared to the method of writing error contents via a device, writing can be done in a shorter time, and there is also an advantage that a large capacity memory is not required.

As described above, according to the present invention, an efficient defect generation method for simulating medium defects in a pseudo defect storage device simulating a magnetic storage medium can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a pseudo disk device showing an embodiment of the present invention, and FIG. 3 is a system block diagram showing the configuration of an embodiment of the present invention.
FIG. 3 is a flow diagram showing the process of sending data. CPU・・・Central processing unit, CHC・・・・・・
Channel device, DPC...Magnetic disk control device, SVP...Service processor, 1...
... Pseudo disk device, 2 ... Pseudo disk unit, 3 ... IC memory, R2 ...
・Error゜Data register, R3, R3'...
Error data register, AC...address counter.

Claims (1)

[Claims] 1. An IC memory is used in place of a magnetic storage medium such as a magnetic disk device connected to a channel device, and an address counter that counts clock signals as a medium address is used, so that the address instruction from the channel device and the address counter can be exchanged. A pseudo external storage device that reads and writes to an IC memory based on a match is provided with an error data register that stores error data and an error address register that specifies an error address, so that an Error information is written to the error data register and error address register, and when the error address register and address counter match, the contents of the error data register are replaced with IC memory read data by the read signal from the channel device. A pseudo-error sending method characterized by sending.