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JPS5919314B2 - Electronic clock with computer - Google Patents
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JPS5919314B2 - Electronic clock with computer - Google Patents

Electronic clock with computer

Info

Publication number
JPS5919314B2
JPS5919314B2 JP51059628A JP5962876A JPS5919314B2 JP S5919314 B2 JPS5919314 B2 JP S5919314B2 JP 51059628 A JP51059628 A JP 51059628A JP 5962876 A JP5962876 A JP 5962876A JP S5919314 B2 JPS5919314 B2 JP S5919314B2
Authority
JP
Japan
Prior art keywords
circuit
computer
oscillation
electronic
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51059628A
Other languages
Japanese (ja)
Other versions
JPS52143069A (en
Inventor
忠彦 中桐
稔 名取
宏 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP51059628A priority Critical patent/JPS5919314B2/en
Priority to US05/796,566 priority patent/US4268913A/en
Priority to GB20856/77A priority patent/GB1569022A/en
Priority to DE19772722598 priority patent/DE2722598A1/en
Publication of JPS52143069A publication Critical patent/JPS52143069A/en
Publication of JPS5919314B2 publication Critical patent/JPS5919314B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G17/00Structural details; Housings
    • GPHYSICS
    • G04HOROLOGY
    • G04CELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C3/00Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
    • G04C3/001Electromechanical switches for setting or display
    • G04C3/005Multiple switches
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G19/00Electric power supply circuits specially adapted for use in electronic time-pieces
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G9/00Visual time or date indication means
    • G04G9/0064Visual time or date indication means in which functions not related to time can be displayed
    • G04G9/007Visual time or date indication means in which functions not related to time can be displayed combined with a calculator or computing means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H2300/00Orthogonal indexing scheme relating to electric switches, relays, selectors or emergency protective devices covered by H01H
    • H01H2300/016Application timepiece

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)
  • Calculators And Similar Devices (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【発明の詳細な説明】 本発明は電子計算機付腕時計に関するものである。[Detailed description of the invention] The present invention relates to a wristwatch with an electronic computer.

近年、液晶、発光ダイ゜オート、あるいはエレクトロク
ロミック物質等の電子光学的、表示装置を用い、時刻を
ディジタルで表示する腕時計が急速に発達し、集積回路
の発達とともに小型化多機能化が計られ、長寿命化等も
十分実用に耐え得るものとなつている。例えば、液晶を
表示に用いた水晶発振式ディジタル腕時計の電池寿命は
すでに2年が普通となつている。一方電子式卓上計算機
も前記腕時計同様集積回路の発達とゝもに、小型化、更
には多機能化、が計られ、表示装置にも液晶等の小電力
表示装置が用いられるようになつた。本発明は上記電子
計算機と、ディジタル表示式腕時計の共通点に着目しデ
ィジタル式腕時計と電子式卓上計算機とを同一腕時計ケ
ースに収納し同一表示装置に時刻及び計算機能とを表示
できる電子計算機付腕時計の電子計算機部分の電力消費
を節約するためのものである。第1図は本発明の電子計
算機付電子時計のシステムブロック図で、1はディジタ
ル時計システムであり発振回路2分周器3計数器4駆動
回路6電源7等より大略構成されている。
In recent years, wristwatches that display the time digitally using electro-optical display devices such as liquid crystals, light-emitting diodes, or electrochromic materials have rapidly developed, and with the development of integrated circuits, they have become smaller and more multifunctional. , long life, etc. are also sufficient for practical use. For example, the battery life of a crystal oscillation type digital wristwatch that uses liquid crystal for its display is already two years. On the other hand, electronic desktop calculators, like wristwatches, have become smaller and more functional with the development of integrated circuits, and low-power display devices such as liquid crystals have come to be used for display devices. The present invention focuses on the common features between the above-mentioned electronic calculator and a digital display wristwatch, and provides a wristwatch with an electronic calculator that can house the digital wristwatch and the electronic desktop calculator in the same wristwatch case and display the time and calculation functions on the same display device. This is to save power consumption of the electronic computer part of the computer. FIG. 1 is a system block diagram of an electronic timepiece with a computer according to the present invention, and 1 is a digital timepiece system, which is roughly composed of an oscillation circuit, 2 frequency dividers, 3 counters, 4 drive circuits, 6 power supplies 7, and the like.

一方電子計算機10のシステムは演算用発振回路11、
演算回路12、表示装置13、電源装置20、置数キー
演算キー等よりなるキーボード16より大略構成されて
いる。前記電子計算機10の電源装置20は、電池18
、昇圧用発振回路14、昇圧回路15から成つている。
On the other hand, the system of the electronic computer 10 includes a calculation oscillation circuit 11,
The keyboard 16 is generally composed of an arithmetic circuit 12, a display device 13, a power supply device 20, and a keyboard 16 including number keys, calculation keys, and the like. The power supply device 20 of the computer 10 includes a battery 18
, a boosting oscillation circuit 14, and a boosting circuit 15.

21はキーボードと協働して演算用発振回路11及昇圧
用発振回路14の動作を匍卿し電子計算機部での電力消
費をできるだけ節減するための制御回路で、第2図a、
bにその構成の一実施例を示す。
Reference numeral 21 denotes a control circuit for controlling the operation of the arithmetic oscillation circuit 11 and the boosting oscillation circuit 14 in cooperation with the keyboard to reduce power consumption in the computer section as much as possible;
An example of the configuration is shown in FIG.

第2図aはマトリクスキーボードの入力検出回路22で
バッファ回路も含まれる。
FIG. 2a shows the input detection circuit 22 of the matrix keyboard, which also includes a buffer circuit.

タイマー回路23、発振周波数変換回路24よりなり、
該発振周波数変換回路24は、演算用発振回路11、昇
圧用発振回路14の発振周波数を変えるか又は発振停止
の状態から発振状態にする。即ちキーボードが動作した
ことを検出してタイマー時間だけ発振回路を発振をさせ
るか、低い発振周波数を高い発振周波数に変換する。第
2図bは電子計算機のキーボード入力信号を検出回路2
2からの信号により、タイマー回路23を作動し該タイ
マー回路23からの信号により電子計算機の電源をタイ
マー時間のみ0n状態にしておく方式である。
Consisting of a timer circuit 23 and an oscillation frequency conversion circuit 24,
The oscillation frequency conversion circuit 24 changes the oscillation frequency of the arithmetic oscillation circuit 11 and the boost oscillation circuit 14, or changes the oscillation frequency from the stopped oscillation state to the oscillation state. That is, it detects that the keyboard is operated and causes the oscillation circuit to oscillate for a timer period, or converts a low oscillation frequency to a high oscillation frequency. Figure 2b shows a circuit 2 for detecting keyboard input signals of an electronic computer.
In this system, the timer circuit 23 is activated by the signal from the timer circuit 2, and the power supply of the electronic computer is kept in the ON state only for the timer period by the signal from the timer circuit 23.

第3図に第2図aに示したプロツク図をやX具体化した
一実施回路図を示すマトリツクスキーボード装置16に
於る線K1〜K4には直流レベルの電圧がかXり線T2
〜T6には位相の異るパルス電圧がかkつているからキ
ーボード16上のいずれかのキーを操作すると線K1〜
K4上にクロツクパルス電圧が加わり、したがつて0R
ゲートからなる人力検出回路22にはキーボード16上
のキーを押すことにより必ずクロツクパルス電圧が現わ
れフリツプフロツプ26及タイマー回路23に人力され
る。
FIG. 3 shows an implementation circuit diagram which is a more specific implementation of the block diagram shown in FIG.
Since pulse voltages with different phases are applied to ~T6, when any key on the keyboard 16 is operated, the line K1~
A clock pulse voltage is applied on K4 and therefore 0R
When a key on the keyboard 16 is pressed, a clock pulse voltage always appears in the human input detection circuit 22 consisting of a gate, and is applied to the flip-flop 26 and the timer circuit 23.

クロツクパルスは普通60Hz程度のものでありタイマ
ーには例えば30秒〜1分程度のカウンターを用いても
よい。入力検出回路22からのクロツクパルスによりフ
リツプフロツプ26は反転し演算用発振回路11及昇圧
用発振回路14を発振させ演算回路12を動作させるタ
イマー回路23はキーボードからのクロツクパルス入力
が無くなつてから所定の時間後に出力を出しフリツプフ
ロツプ26を反転させて演算用発振回路11及昇圧用発
振回路14の発振を停止するか、もしくは周波数の低い
状態にする。第4図は昇圧用発振回路14に本発明の制
御装置を用いたもので、フリツプフロツプ26の出力信
号によりトランジスタ27が0n.0ffして発振回路
14を発振状態あるいは停止状態にすることができる。
The clock pulse is normally about 60 Hz, and the timer may be a counter of about 30 seconds to 1 minute, for example. The flip-flop 26 is inverted by the clock pulse from the input detection circuit 22, causing the calculation oscillation circuit 11 and the boost oscillation circuit 14 to oscillate, and the timer circuit 23 which operates the calculation circuit 12 to operate the calculation circuit 12 for a predetermined period of time after the clock pulse from the keyboard is no longer input. Afterwards, the output is output and the flip-flop 26 is inverted to stop the oscillation of the calculation oscillation circuit 11 and the boost oscillation circuit 14, or to set the frequency to a low state. In FIG. 4, the control device of the present invention is used in the boost oscillation circuit 14, and the output signal of the flip-flop 26 causes the transistor 27 to turn on. 0ff, the oscillation circuit 14 can be brought into an oscillating state or a stopped state.

第5図は電源回路をキーボード出力22a及タイマー出
力23aによりフリツプフロツプ26を介してトランジ
スタ28を0n,.0ffすることにより電子計算機全
体の電力供給を停止する場合である。又タイマー回路2
3を用いることにより一定時間以上電子計算機に電力を
供給することがないため電子計算機部の使用後電源スイ
ツチを0ffにしなくても自動的に電源が切れることが
なく、電池の消耗を少くすることができる等の効果が大
きい。
In FIG. 5, the power supply circuit is configured such that the transistors 28 are turned on, . This is a case where the power supply to the entire computer is stopped by turning it off. Also timer circuit 2
By using 3, power is not supplied to the computer for more than a certain period of time, so the power does not turn off automatically even if the power switch is not turned off after using the computer section, reducing battery consumption. It has great effects, such as being able to

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の電子計算機付腕時計を示し、第1図はそ
のプロツク図、第2図A,bは電子計算機部の電力節減
方式のプロツク図、第3図は、電力節減方式の一実施例
を示す図、第4図は、発振器部スイツチ方式の一実施例
を示す回路図、第5図は、電源部のスイツチ方式の一実
施例を示す回路図である。 16・・・・・・キーボード、21・・・・・惰(イ)
回路、22・・・・・・入力検出回路、23・・・・・
・タイマー回路、26・・・・・・フリツプフロツプ、
27,28・・・・・・トランジスタ。
The drawings show a computer wristwatch according to the present invention, FIG. 1 is a block diagram thereof, FIGS. 2A and 2B are block diagrams of a power saving method for the computer section, and FIG. 3 is an embodiment of the power saving method. FIG. 4 is a circuit diagram showing an embodiment of the oscillator section switch method, and FIG. 5 is a circuit diagram showing an embodiment of the power supply section switch method. 16...Keyboard, 21...Inertia (a)
Circuit, 22... Input detection circuit, 23...
・Timer circuit, 26...Flip-flop,
27, 28...transistor.

Claims (1)

【特許請求の範囲】[Claims] 1 電子計算機付電子時計に於て、電子計算機の操作キ
ーのマトリクス線群の一部を入力とするキー入力検出回
路と、電子計算機の電源を供給するための2種類の発振
周波数を有する昇圧用発振回路と、前記キー入力検出回
路の出力によつて前記発振周波数を高く保持し、タイマ
ー回路によつて低く保持するためのフリップフロップ回
路と、前記昇圧用発振回路によつて2種類の電圧を供給
する電子計算機の電源用昇圧回路と、該昇圧回路の出力
によって制御される電子計算機の演算用回路と、を有す
ることを特徴とする電子計算機付電子時計。
1. In an electronic watch with a computer, a key input detection circuit that receives part of the matrix line group of the operation keys of the computer as input, and a booster circuit that has two types of oscillation frequencies to supply power to the computer. An oscillation circuit, a flip-flop circuit for keeping the oscillation frequency high by the output of the key input detection circuit and low by a timer circuit, and two types of voltages are generated by the boost oscillation circuit. An electronic timepiece with an electronic computer, characterized in that it has a booster circuit for supplying a power supply to an electronic computer, and an arithmetic circuit for the electronic computer that is controlled by the output of the booster circuit.
JP51059628A 1976-05-18 1976-05-25 Electronic clock with computer Expired JPS5919314B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP51059628A JPS5919314B2 (en) 1976-05-25 1976-05-25 Electronic clock with computer
US05/796,566 US4268913A (en) 1976-05-18 1977-05-13 Electronic calculator watch
GB20856/77A GB1569022A (en) 1976-05-18 1977-05-18 Electronic calculator watch
DE19772722598 DE2722598A1 (en) 1976-05-18 1977-05-18 ELECTRONIC CLOCK COMBINED WITH A COMPUTER

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51059628A JPS5919314B2 (en) 1976-05-25 1976-05-25 Electronic clock with computer

Publications (2)

Publication Number Publication Date
JPS52143069A JPS52143069A (en) 1977-11-29
JPS5919314B2 true JPS5919314B2 (en) 1984-05-04

Family

ID=13118678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51059628A Expired JPS5919314B2 (en) 1976-05-18 1976-05-25 Electronic clock with computer

Country Status (1)

Country Link
JP (1) JPS5919314B2 (en)

Also Published As

Publication number Publication date
JPS52143069A (en) 1977-11-29

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