JPS5920182B2 - Tape speed display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tape speed display circuit capable of digitally displaying tape speed deviations.

In a tape recorder, it is desirable that the tape always run at a constant speed, but due to changes in load, etc., the motor rotation speed changes, which in turn changes the flywheel rotation speed, resulting in tape speed. The speed may deviate from the normal speed.

The present invention provides a tape speed display circuit that can accurately display such tape speed deviations, and the present invention will be described below with reference to the drawings.

1 is a reference signal generator that generates a reference frequency signal, and usually uses a crystal oscillator.

A frequency divider 2 divides the frequency of the reference frequency signal, and in the present invention, the frequency of the reference frequency signal is divided by 1/1000.

3 is a second frequency divider that further divides the frequency of the signal A divided by 5 into 1/2, and 4 is a rotation speed detector which detects the rotation speed of the flywheel which exhibits the rotation speed most closely related to the tape speed passing through the magnetic head. A thin magnet is attached around the periphery, and a Hall element is provided opposite the magnet to extract a pulse signal corresponding to the number of rotations of the flywheel.

5 is a third frequency divider that divides the frequency of the extracted pulse signal so that it can be compared with the signal A of the first frequency divider 2; 6 is a reset pulse oscillator; 5
A reset pulse signal R is generated at the falling edge of the pulse signal generated by 5, and the reference signal generator 1 and the first and second frequency dividers 2 and 3 are reset.

7 is a phase comparison circuit, a first exclusive OR circuit 8 to which the signals of the first and second frequency dividers 2 and 3 are applied;
A second exclusive OR circuit 9 to which the signals of the frequency dividers 2 and 5 are added, either directly or via an inverter 10 to the first and second
It consists of a first NAND circuit 11 to which the outputs of exclusive OR circuits 8 and 9 are added.

12 is an inverter; 13 is a second NAND circuit that receives the output of the inverter 12 and the signal output from the reference signal generator 1; 14 is a counter;
A blanking terminal connected to the inverter 12
It generates the set pulse signal H based on the signal from the controller, is connected to the set pulse generator 15, and is connected to the set terminal r.
, and further has an input terminal 1n.

16 is a phase discrimination circuit, and third and fourth NAND circuits 17,1
8, an isoverter 19 and a flip-flop 20.

Reference numeral 21 denotes a display device consisting of a numeric display section 22 and a +/1 display section 23.

Next, the operation of the present invention will be explained.

A reference frequency signal D from a reference signal generator 1 is divided by a first frequency divider 2 to generate a signal A, which is further divided by a second frequency divider 3 to generate a signal B. On the other hand, the signal E detected by the rotation speed detector 4 is divided by the third frequency divider 5 and the signal C
occurs. These signals are applied to the phase comparison circuit 7, and if the flywheel is rotating at a specified speed, the output will be at level 61''. That is,
As can be seen from FIG. 2, the signals have a relationship as shown in the table below.

In the first state, the output of the first exclusive OR circuit 8 is level L/"01, so the output of the first NAND circuit 11 becomes level "1", and in the second state, the output of the first NAND circuit 11 is level "1". Since the output of exclusive OR circuit 9 is at level 611, a signal at level 101 is applied to first NAND circuit 11 via inverter 10.

Therefore, the output of the first NAND circuit 11 is at level "1". Also, in the third state, the output of the first NAND circuit 11 is at level "11" as in the second state.

Further, in the fourth state, as in the first state, the output of the first exclusive OR circuit 8 is at the level "O", so that the output of the first NAND circuit 11 is at the level "1". When the flywheel is rotating at the specified speed in this manner, the output of the phase comparison circuit 7 is always at level "1". Therefore, the second NAND circuit 13 via the inverter 12
Since the signal level added to 4 is "0", the output of the second NAND circuit 13 is always at the level "1",
Since no pulse signal is applied to the counter 14. The counter 14 does not count, and the numerical display section 22 of the display 21 displays that the speed deviation is 0. Next, suppose that the speed of the flywheel becomes faster than the specified speed.

The states of each signal at that time are shown in FIG. 3 and the following table. What differs here from the above is that a third state has been added.

This third state is because the speed of the flywheel is higher than the specified speed, so the signal C quickly becomes level "1".
During this time, the output of the first exclusive OR circuit 8 is at level "1" and the output of the second exclusive OR circuit 9 is at level "01", so
The output of the first NAND circuit 11, that is, the level of the phase comparison circuit 7 becomes 60''.
1" and is first applied to the set pulse generator 15 to generate a reset pulse signal H, which resets the counter 14.The signal G is also applied to the second NAND circuit 13, so if When the level of the reference frequency signal from the reference signal generator 1 becomes "1", it has been level 6.
The output of the second NAND circuit 13, which was 1 signal, is at level “O”
becomes. Next, when the level of the reference frequency signal becomes 601, the output of the second NAND circuit 13 becomes level "1". This is done every time the reference frequency signal arrives, so
Eventually, a pulse signal equal to the reference frequency signal is applied to the input of the counter 14 for counting. This continues while each signal A, B, C is in the third state.

Since the time in the third state is proportional to the deviation in the number of rotations of the flywheel, the number counted by the counter 14 becomes the deviation in the number of rotations, which is converted into a percentage and the number on the display 21. It is displayed on the display section 22. The signal of level 611 converted by the inverter 12 is sent to the third and fourth NAND circuits 17 of the phase identification circuit 16.
Added to 18. Meanwhile, at the same time, signal A is also applied to the third and fourth NAND circuits 17 and 18. Then, since the inputs of the fourth NAND circuit 18 are both at level 611, the output is at level "07," but since the signal A is applied to the third NAND circuit 17 via the inverter 19, the output is at level T'. As a result, the flip-flop 20 is set to display the + side of the +1 display section 23.Conversely, if the speed of the flywheel is slower than the specified value,
The states of each signal at this time are as shown in FIG. 4 and the table below.
As can be seen, the only difference is the third state and the other states are the same.

This is because the rotational speed of the flywheel is lower than the specified speed, so there is a delay in the signal (C) changing from level "0" to level "1". At this time, since the output of the first exclusive OR circuit 8 is at level "1" and the output of the second exclusive OR circuit 9 is at level "O", the output of the first NAND circuit 11 is at level "00" as before. Become.

Therefore, after the counter 14 is reset, it counts the pulse signals generated by the second NAND circuit 13. The number counted by the counter 14 indicates the percentage of rotation speed deviation, and is displayed on the numerical display section 22. On the other hand, since the phase discrimination circuit 16 receives the signal of level "1" converted by the inverter 12 and the signal (4) of level 10" at that time, the output of the fourth NAND circuit 18 becomes level 61", and + One side of one display section 23 will be displayed.

As described above, the tape speed display circuit of the present invention uses a phase comparator to divide the signal obtained by dividing the reference frequency signal and the signal obtained by dividing the signal detected from the rotating body related to the tape speed. A special state of each of the signals that occurs when the rotational speed of the rotating body deviates from a specified speed is detected, a gate circuit is turned on during that period using the detected signal, and the reference frequency signal is used as a counter. Since the tape speed is additionally counted, the discrepancy in tape speed can be easily displayed digitally.

Moreover, the phase identification circuit generates different signals when the rotational speed of the rotating body is ahead or behind the specified speed, so it is displayed whether the rotational speed of the rotating body is ahead or behind the specified speed. You can also do that.

[Brief explanation of the drawing]

Figure 1 is a tape speed display circuit diagram of the present invention, Figures 2-
FIG. 4 is an output signal waveform diagram in each state of the present invention. 1... Reference signal generator, 2... First frequency divider, 3... Second frequency divider, 4... Rotation speed detector, 5...Third frequency divider, 7...
Phase comparison circuit, 14... Counter, 16...
... Phase discrimination circuit, 20 ... Flip-flop, 21 ... Display device.

Claims (1)

[Claims] 1. A reference signal generator that generates a reference frequency signal, first and second frequency dividers that divide the reference frequency signal, and a rotation speed that detects a signal corresponding to the rotation speed of a rotating body related to tape speed. a detector, a third frequency divider that divides the detected signal to the same degree as the signal divided by the second frequency divider, and each state of the first, second, and third frequency dividers; A phase comparator that compares the signals and generates a pulse signal according to the deviation when the rotational speed of the rotating body deviates from a specified speed, and a pulse signal that is controlled by the pulse signal from the phase comparator and generates a pulse signal. a gate circuit that applies a reference frequency signal to a counter during a period of time; a phase identification circuit that compares the signal from the phase comparator and the signal from the first frequency divider to identify whether the rotational speed of the rotating body is advanced or delayed; A tape speed display circuit comprising the counter and a display operated by a signal from the phase identification circuit.