JPS5921069B2 - Program writing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program writing method for a program-writable electronic desktop calculator or the like.

In general, in electronic desktop calculators (hereinafter referred to as program calculators) on which programs can be written, if a program is written to consecutive addresses in the program memory and a missed write is discovered during debugging, etc. It is necessary to interrupt and insert a program step.
To insert this interrupt, operate the program write switch to set the program write mode, specify the address in the program memory that corresponds to the missed write, and then operate the shift key to erase the subsequent program data. After shifting backward one address at a time, interrupt data is written by operating the input key. However, in order to process the program data after the interrupt data, a special shift key must be provided, and the necessity of operating the shift key makes the interrupt operation complicated. The present invention has been made to eliminate the above-mentioned drawbacks, and provides a new program writing method that allows program interrupt operations to be performed in the same manner as normal program writing operations.

An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, the program write input unit 11 is configured to input program write data by operating a tick key, function key, etc. in a state where the program write mode is set by operating a program write key on a keyboard unit (not shown). and generates an address memory read command signal. The write data is led to buffer memory 12. This buffer memory 12 generates a step pulse every time data is input. This step pulse passes through the OR gate 13 and is led as a step input to the address counter 14. The count output of this counter 14 is the program memory 15.
Directed as a hair addressing input. Further, the step pulse obtained from the buffer memory 12 increments the address counter 14 and then gives a read command R to the program memory 15 via the delay circuit 16. Further, the output pulse of the delay circuit 16 is guided to the program memory 15 via the delay circuit 17 as a write command w. That is, after reading out the contents of the program memory 15 at an address designated by a signal from the program write input unit 11 to which input data is to be written by a read command R, the input data stored in the buffer memory 12 is read out by a write command w. This is what is written to that address. The read output data of the program memory 15 is led to a display 18, a data detection circuit 19, and a buffer memory 20. The data detection circuit 19 detects the presence or absence of data read from the program memory 15 and generates a ``data present'' 2 output or a ``data not present'' 7 output. This two data outputs are led to the buffer memory 20 as a read command. The read output data of this buffer memory 20 is input to the buffer memory 12, and the memory data of this buffer memory 12 becomes the write input of the program memory 15. Further, the data no output 7 output of the data detection circuit 19 is led to the address counter 14 as a read command input.
The count output of this address counter 14 is led to the address memory 21 as read input data, and the memory address of this address memory 21 is input to the address counter 14.
as read input data. Then, as a read command for the address memory 21, an address memory read command signal output from the program write input section 11 is introduced via a delay circuit 22. In addition, the or gate 13
A step pulse generated every time an address shift key (not shown) is operated is introduced. Now suppose that it is desired to write a program into the program memory 15, for example, as shown in FIG.

That is, corresponding to addresses 1 to 8, data Prl...:
and write data 4 corresponding to addresses 9 to 16.
.= is written, data 2...x is written corresponding to addresses 17-24, and 3...: is written corresponding to addresses 25-28. In addition, among the above language data, Prl
Function data such as , : are written by operating the corresponding function keys, and numerical data such as 1 and 2 are written by operating the corresponding numeric keys.

Here, the meaning of each data in the above program will be explained.

Prl indicates the number of a plurality of divided areas in the program memory 15 by a subscript, and the subscript 1 indicates area 1 including the address where the program of FIG. 3 is written. E
NTl:2:3: indicates that three types of variables are sequentially input as input variable data, and each is handled as a variable of 2'' and 3''. The ":" mark indicates a break.ゞ4'', ゞ5'', ゞ6'' respectively represent calculation output data, and as shown in Figure 3, the calculation output data of ゞ4I is the multiplication result of variables ゞbi and ゞ2'', and similarly ゞ5″ and ゞ6″ are respectively ゞpi and ゞ3″, ゞbi and ゞ3
is the result of multiplication of ``.'', - means "equal", x means "multiplication", and N means "answer".

Therefore, the meaning of the program that writes to the memory area 1 is ``input variable data 1, 2, and 3 are stored in data registers 1, 2, and 3, respectively (not shown).

). Then, calculate 1×2 and calculate output data 4
Put it into memory register 4. Also calculate 2×3 and put the calculation output data 5 into the memory register 5. Also 1×
3 and put the calculation output data 6 into the memory register 6. Then, display the calculation output data 4 stored in the memory register 4 as an answer. ..." is. Now suppose that a program has been written by mistake as shown in FIG.

That is, compared to the correct program shown in FIG. 3, the program shown in FIG. 2 fails because variable data 3 at address 19 is omitted, and each piece of data after this variable data 3 is incremented by one address and written. Such writing omissions in a program are discovered during debugging work, and the interrupt operation for writing omission data will be explained in detail below. First, a step pulse is generated by operating an address shift key (not shown).

This step pulse passes through the OR gate 13 and is input to the address counter 14, causing the counter 14 to step. Then, the operation of the address shift key is repeated until the specified address of the address counter 14 becomes 18, which is one place before the write-missed data address 19. Confirmation of the specified address is possible because each read data at addresses 1 to 18 of the program memory 15 is sequentially displayed on the display 18. Next, operate the program write switch to set the program write mode, and then operate the numeric keypad 3 in the same way as for normal program write, and the write omission data 3 and address memory read command signal will be sent from the program write input section 11. Occur.

This write omission data 3 is stored in the buffer memory 12. This buffer memory 12 generates a step pulse when inputting data, and this step pulse is input to the rear address counter 14 through the OR gate 13.
advance. Therefore, the address counter 14 specifies the write omission data address 19. Thereafter, the address memory read command signal output from the program write input section 11 is delayed by the delay circuit 22 and input to the address memory 21. Therefore, the address memory 21 stores the designated address (address 19) of the address counter 14. Also, the address counter 14 indicates the write omission data address 1.
9 is specified, the step pulse output of the buffer memory 12 is delayed by the delay circuit 16, and the step pulse output of the buffer memory 12 is delayed by the delay circuit 16.
5 as a read command. Therefore, the data written in the write-missed data address 19 is read out from the program memory 15 and input to the data detection circuit 19, and is also stored in the buffer memory 20. Thereafter, the delayed output step pulse of the delay circuit 16 is delayed by the delay circuit 17 and input to the program memory 15 as a write command. Therefore, write omission data address 1
9, the write-missed data 3 stored in the buffer memory 12 cannot be written. Next, the data detection circuit 19 detects the presence or absence of input data and generates a data presence 2 output, which causes the memory data (data written in the write-missed data address 19) of the buffer memory 20 to be read? and input into the buffer memory 12. Therefore, a step pulse is generated from the buffer memory 12 to increment the address counter 14 to designate the next address 20.

Next, the data 6 at address 20 of the program memory 15 is read out, stored in the buffer memory 20, and also input to the data detection circuit 19. Next, program memory 15
The memory data (data (1) at address 19) of the buffer memory 12 is written to the address 20 of the buffer memory 12. Next, the buffer memory 20 is
memory data (data 6 read from address 20) is input to buffer memory 12. Similarly, each piece of data that was written after address 20 in the program in Figure 2 is automatically moved down one address at a time and written to the next address.
The program is modified as shown in FIG.

Before writing the data at the final address to the next address, the contents at the next address are read from the program memo I river 5. However, in this case, since no program data has been written to the next address, there is no memory input to the buffer memory 20, and the data detection circuit 19 generates a ``no data 2'' output. Therefore, after writing the data at the final address of the program to the next address, there is no data input to the buffer memory 12, and the address counter 14 receives the memory address (address 19) of the address memory 21 due to the no data 2 output. Load. Address 1 of the program memory 15 specified by this address counter 14
Data 9, that is, data 3 newly written by the write correction (see the program in FIG. 3), is displayed on the display 18, and it becomes clear that the write correction has been performed. As described above, in response to the operation of the numeral key 1 or function key 1 to write the write-missed data, the program data subsequent to the write-missed data is automatically moved down one address at a time at high speed.

Therefore, if there are two or more pieces of missing write data in a row, by performing the above-mentioned write correction operations in address order, the data after the write missing data will be automatically moved down for each correction. . In this case, during the second and subsequent corrections, the address counter 1 is set by the previous correction operation.
The designated address No. 4 is automatically set to the address one address before the write-missed data address. That is, address 19, 20
When modifying address 19 by writing, the designated address of address counter 14 is set to address 19 after the address 19 has been modified as described above, and the next address 20 can be modified by writing. In the above embodiment, the address counter 14 is set before writing data to the program memory 15.
Progress? Therefore, before the write correction, the specified address of the address counter 14 is set to the address one address before the write-missed data address.

However, the address counter 14 may be incremented after data is written into the program memory 15 instead of before it is written. In this case, instead of the step pulse output of the buffer memory 12, a step pulse obtained by further delaying the delayed output step pulse of the delay circuit 17 by a delay circuit (not shown) is used, and this step pulse is sent to the OR gate 13. All you have to do is input it. Also, address counter 14 before writing correction
The specified address may be set in advance to the write-missed data address by operating the shift key. Therefore, the address memory 21 stores the write-missed data address specified by the address counter 14 before writing the write-missed data, and the memory address is read by the address counter 14 after writing the final address data. In addition, in the above embodiment, "Prl" indicates the start of an independent program so that the program memory can be arbitrarily divided to write multiple independent programs, but of course, only one program can be stored in the memory. It goes without saying that Prl'' is not necessary if the program is a program, and if multiple programs are each independently fixed length, there will be space at the end of each program in response to an interrupt operation, so the shift operation will be shortened. Of course, various application changes are possible, such as ending the process with . According to the above-mentioned program writing method, when a program interrupts data that has not been written to the program memory written in consecutive addresses, the display that displays the output of the program memory is monitored. The address of the write-missed data is designated by the address counter, and after the data at the address is automatically read, the write-missed data is written at the address by key operation. Then, regarding the data read from the program memory, the address counter automatically specifies the address next to the address where the data was written, reads the data at the address, and then writes the data to the address in the program. Repeat until the end.
Therefore, the process of moving the address of the program data after the write data is carried out in a sentry manner, so compared to the conventional address movement operation by shift key operation and program data rewriting operation by input key operation, the program write A similar operation is often used to write and modify operations, which is extremely convenient.

As described above, the present invention can provide a program writing method that can simplify program writing and modification operations.

[Brief explanation of drawings]

FIG. 1 is a program diagram showing an embodiment of the program writing method according to the present invention, FIG. 2 is a diagram showing an example of the unmodified program written in the program memory of FIG. 1, and FIG. FIG. 2 is a diagram showing an example of a modified program written in the program memory of FIG. 1; 11...Program writing input section, 12, 20.
...Buffer memory, 14...Address counter, 15...Program memory, 19.
...Data detection circuit.

Claims (1)

[Claims] 1. An input section for inputting program information, a program memory into which program information from this input section is continuously written, an address specifying means for specifying a write address of this program memory, and input program information and the above program. a first buffer memory that stores program information to be written to the memory; a second buffer memory that stores program information read from the program memory; and an end of the program information written to the program memory. According to the program end detection means that detects the program end detection means and the program information input from the input section,
A first device that reads program information at a write address designated in advance by the address designation means and writes it into the second buffer memory, and writes program information stored in the first buffer memory to the write address. writing means; after the contents of the first buffer memory are written into the program memory, the address designation of the address designation means is incremented, and the end of the program information is detected by the program end detection means; means for terminating the increment, and writing the program information stored in the second buffer memory into the first buffer memory, and writing the program at the next write address designated by the address designation means. It is characterized by comprising second writing means for reading information and writing it into the second buffer memory, and writing program information stored in the first buffer memory to the next write address. Program writing method.