JPS5853380B2 - Program erase method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program erasing method in, for example, a desktop electronic computer in which a program can be written.

A desk-top electronic calculator (hereinafter referred to as a program calculator) that can generally be programmed.

), when debugging or modifying a program, you can use the program from the first step to intermediate steps that have already been written in the program memory without making any changes, but all subsequent program steps will be erased. Sometimes you want to put it away.

When erasing such a program step, it is desirable to perform the erasure using as simple an operation as possible.

The present invention has been made in view of the above-mentioned circumstances, and uses a normal program end signal to process all steps after an arbitrary step of a program written in a program memory without using a special erase command operation. This provides a program erase method that can automatically erase the program by simply pressing the button.

An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, the keyboard section 11 is provided with a numeric keypad for inputting numerical data, function keys for commanding four arithmetic operations, and program keys used for writing and reading programs.

Here, the program keys mentioned above include an end key used to specify the end of the program, and a step key used to manually advance the program step by step, but the functions of these keys will be explained later. Detailed.

The keyboard section 11 generates key signals in response to the operation of each key.

This key signal is led to an encoder 12 using, for example, a ROM (read only memory), and is converted into input data corresponding to the key signal.

This input data is led to buffer memory 13 and stored.

The data stored in this buffer memory 13 is stored in, for example, RAM (
a random access memory) and a decoder 15.
guided by.

This decoder 15 generates an end pulse output when detecting end data corresponding to the end key, and generates a step pulse output when detecting step data corresponding to the step key.

The end pulse output of the decoder 15 is AND gate 1
6, and the step pulse output is led via an inverter 17 as the other input of an AND gate 18.

Further, the count output of an address counter 190 is led as an addressing input of the program memory 14, and the data output of the program memory 14 is led to a display 20.

On the other hand, a pulse generation circuit 21 is provided which generates a forward pulse every time each key of the keyboard section 11 is operated,
Further, this pulse generating circuit 21 also generates a write pulse every time a key is operated, if the mode key or the like specifies that a program is currently being written in the keyboard section 1.

Further, a clock pulse (see FIG. 2C) generated by a clock generation circuit 22 is inputted to this pulse generation circuit 21.

The advancing pulse (see FIG. 2C) occurs slightly later than the clock pulse, and the write pulse (see FIG. 2C) occurs even later than the advancing pulse and slightly before the next clock pulse.

The output of this write pulse is guided as the other input of the AND gate 18, and the output of this AND gate 18 is guided to the OR gate 23.

Further, the advancing pulse output is guided as the other input of the AND gate 16 and also to the OR gate 24.

The output of the AND gate 16 is directed as an SR flip-flop 250 set input.

The Q output of this flip-flop 25 is 26
, 27 as well as to the delay circuit 28.

This delay circuit 28 delays the Q output of the flip-flop 25 by a predetermined time (for example, so as to lag behind the write pulse generated after the end key is operated).

Further, the clock pulse output from the clock pulse generating circuit 22 is led to a delay circuit 29, where it is delayed by a predetermined time (for example, 1/2 degree of the clock period).

The outputs of the delay circuit 29 and the delay circuit 28 are led as inputs to the AND gate 27, and the output of the AND gate 27 is led to the clear input terminal of the buffer memory 13 and also to the OR gate 23.

The output of this OR gate 23 is the output of the program memory 14.
is derived as a read/write (R/W) command input.

Here, the "■" level of the output of the OR gate 23 serves as a write command, and the "O" level serves as a read command.

Further, the clock pulse output is guided as the other input of the AND gate 26, the output of this AND gate 26 is guided as an incremental input to the address counter 19, and the output of each stage of this counter 19 is input to each input of the AND gate 30. guided as.

The output of this AND gate 30 is the flip-flop 2
5 as the reset input.

Now, the program memory 14 has consecutive addresses, for example 1.
Assume that program data is written at addresses ~n.

It is assumed that among the program data, the steps from the first step to the intermediate steps are left as they are, and the subsequent steps are deleted.

Since this program erase operation is normally performed during debugging, the keyboard section 11 is designated to be in a program writing mode, and therefore the pulse generation circuit 21 generates a progress pulse and a write pulse every time a key is operated. A pulse is output.

First, when a step key on the keyboard section 11 is operated, a key signal corresponding to this key is led to the encoder 12 and converted into step data.

This step data is stored in the buffer memory 13,
The step data output of this memory 13 is detected by a decoder 15.

Step pulse output of this decoder 15 (1” level).

) is inverted to the ``0'' level by the inverter 17,
The gate is closed by being guided by the AND gate 18.

Therefore, one write pulse (“1” level) is generated by operating the step key.

) is prohibited from passing through the ANDCATE 18.

On the other hand, the flip-flop 25 is cleared in the initial state.

Further, when step data is generated by operating a step key, the decoder 15 does not detect end data, so it does not generate an end pulse output, and the end data output terminal is at the nOn level.

Therefore, the AND gate 16 closes the gate,
Since its output is "0" level, the flip-flop 25 has a set input ("1" level).

) is not guided. That is, the Q output of the flip-flop 25 is at the OII level and closes the gates 26 and 27.

Therefore, the OR gate 23 to which the "O" output of the AND gate 27 and the "O" output of the AND gate 18 are guided generates the "OII output" and outputs the "O" output to the program memory 14.
Give read command to.

Note that the buffer memory 13 is not cleared by the '0' output of the AND gate 27.

Furthermore, one le progression pulse ("l" pulse) is generated by operating the step key.

) is led to the address counter 19 as an increment input through the ORKATE 24.

Here, if the count output of the address counter 190 is O in the initial state, the count output becomes 1 due to the step input.

Therefore, address 1 is designated for the program memory 14,
The program step at address 1 is read out and displayed on the display 2.
Displayed as 0.

That is, first the first step of the program is displayed.

Thereafter, each time the step key is operated, the second and subsequent steps of the program are sequentially read out and displayed.

Assume that the count output of the address counter 190 becomes f, for example, in this way, and the step at address f of the program memory 14 is read out and displayed.

The program steps displayed so far remain in the program memory 14 as they are.

It is also assumed that the steps after the above steps are unnecessary.

Then, operate the end key once. Through this operation, a key signal corresponding to the end key is guided to the encoder 12 and converted into end data.

This end data is input to the buffer memory 13.

Therefore, the decoder 15 does not detect step data but instead detects end data and outputs an end pulse of "1'" level (see FIG. 2g).

) occurs. This end pulse output and the advancing pulse match in timing and satisfy the AND condition of the AND gate 16, and the AND gate 16 generates a "1" output and sets the flip-flop 25.

Therefore, the Q output of the 7-rip 70-tube 25 becomes the "1" level as shown in Figure 2e, and the
7 and delay circuit 28.

Incidentally, the advancing pulse generated by operating the end key is input to the OR gate 24.

The above-mentioned traveling pulse (
See second diagram.

) increments the address counter 19, and this counter 1
The count output of 9 becomes (f+1) and specifies the address (f+1) of the program memory 14.

Further, since the decoder 15 does not generate a step pulse output, the step pulse output terminal is at the 0'' level.

This '0' level is inverted by the inverter 17 and guided to the AND gate 18.

Therefore, a write pulse generated after the advance pulse is guided to the OR gate 23 through the AND gate 18.

The "1" output of this OR gate 23 (see Figure 2g).

) is input to the program memory 14 as a write command,
Among the outputs of the OR gate 23, end data, which is data stored in the buffer memory 13, is written to address (f+1) of the program memory 14 by the write pulse.

The first clock pulse that occurs after the write pulse then passes through an AND gate 26 to which the Q output ++ 199 of the flip-flop 25 is led, and then through an OR gate 24 to increment the address counter 19.

Therefore, the count output (f+2) of the counter 19 specifies the program memory 140 address (f+2).

On the other hand, the clock pulse is delayed by a delay circuit 29 for a predetermined time, and the Q output of the flip-flop 25 is delayed by a delay circuit 28 for a predetermined time.

Then, the output of the delay circuit 28 (see FIG. 2g).

), the output of the delay circuit 29 (see FIG. 2g), and an AND condition is established in the AND gate 27 to which the Q output of the flip-flop 25 is input.

The '1' output of the AND gate 27 is led to the OR gate 23 and also to the buffer memory 13 as a clear input.

Therefore, the end data stored in the buffer memory 13 is cleared, and the contents of the buffer memory 13 are expressed as "no data" (for example, zero suppression code data).

become.

Then, the zero suppress code data in the buffer memory 13 is written to the address (f+2) of the program memory 14 by the OR gate 230'''1'' output.

Thereafter, in the same manner, the clock pulse passes through the AND gate 26 and the OR gate 24, sequentially increments the address counter 19, and sequentially designates the address of the data to be erased in the program memory 14 (.

Each time this address is specified, the clock pulse passes through the delay circuit 29, AND gate 27, and OR gate 23, and writes zero suppression data into the program memory 14.

Then, the count output of the address counter 19 is the maximum value n
When the final address n of the data to be erased in the program memory 14 is specified, each input of the Android game 30 becomes "1" and the AND output becomes "1".

This AND output "1" resets the flip-flop 25, and the Q output becomes O)).

Since this Q output "O" closes the AND gate 26 and prohibits passage of the clock pulse, the counter 19 maintains the state of the count output n thereafter.

Further, the Q output "0" is delayed by the delay circuit 28 and inputted to the AND gate 27, and by closing the AND gate 27, writing input to the program memory 14 is cut off thereafter.

However, while the Q output "0" is delayed by the delay circuit 28, the delayed output clock pulse of the delay circuit 29 passes through the AND gate 27, further passes through the OR gate 23, and writes zero suppression data to address n of the program memory 14. It's crowded.

In the above embodiment, the end data is written after incrementing the address counter by operating the end key and specifying the address of the program memory where the end data should be written. It goes without saying that the circuit configuration can be changed so that the end data is written after specifying the address to which the data is to be written, and the next address in the program memory is specified after the end data is written.

Furthermore, the timing of supplying the clear signal to the buffer memory 13 may be variously considered in addition to the above embodiments.
Write and read instructions for the memory 14 are issued by the OR gate 23,
It goes without saying that it can be realized not only by the AND gate 27, the delay circuit 28, etc., but also by various other technical means, and other circuit components can also be modified in various ways without departing from the gist of the present invention. It is.

According to the program erasing method described above, the steps from the first step to intermediate steps of the program written in consecutive addresses in the program memory are read out in address order by operating the step keys and displayed on the display. By operating the end data, end data is written following the program step that should be left in the program memory in the program, and the program after this step is automatically sequentially erased.

Therefore, it is possible to generate an erase command by simply operating the end key, which is normally used when instructing the end of a program, and automatically erase the program from any step in the program, making the erase operation extremely easy. It is simple and does not require a special key to instruct erasure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the program/erase method according to the present invention, and FIGS. 2a to 2i are timing charts shown to explain the operation of FIG. 1. 11...Keyboard section, 12...Encoder, 13゛''°゛°°buffer memory, 14...
...Program memory, 15...Decoder,
16, 18, 26° 27.30...And gate, 19...Address counter, 20...
...Indicator, 23, 24...Or gate, 25
...Flip-flop, 28, 29...
・Delay circuit.

Claims (1)

[Claims] 1 a memory capable of writing each step of a program at consecutive addresses; a means for sequentially specifying and reading and displaying each step of the program written in this memory; and a means for generating predetermined data by operating a predetermined key, means for writing the predetermined data at a desired address of the predetermined data, and means for automatically sequentially specifying and erasing programs written at addresses subsequent to the address of the predetermined data written by the means. This program erase method is characterized by: