JPS592106B2 - Cyclic memory guide - Google Patents

Description

[Detailed description of the invention] The present invention relates to a cyclic memory control scheme.

Cyclically operated memories are indispensable for holding memories for opening and closing switches in time-division exchanges or for time-division multiplex processing units, and have become widely used in recent years. In order to cause this type of cyclic memory to operate cyclically, an address expressed in a natural binary code that changes cyclically is generated and the memory is controlled using this address.

The reason why natural binary codes are widely adopted is that natural binary code counters can be easily realized, and cyclic
If the memory has an interface with the processing device and the processing device controls data writing into the cyclic memory, natural binary code representation is easier to process due to the structure of the processing device.

Recently, MOS IC memories have become widely used as cyclic memory elements.

MOS IC memory has advantages over conventional bipolar memory in that it is cheaper and consumes very little power.Nowadays, as elements become more integrated and devices themselves become more compact, lower power consumption is becoming more and more popular. Along with low cost, this is one of the extremely important factors in equipment design.
reality is possible. The reason why the power consumption of the MOS IC memory is low is that it is itself a voltage-controlled element and is designed to consume power only during dynamic operations such as address switching.

For example, when using MOS IC memory as the main memory of a processing device, the main memory only has a - address specified at one time, and two or more addresses are not specified at the same time, so even if the memory has a large capacity, it will operate at a certain point in time. Effectively, only a small portion of the memory elements are used. In this way, there is an effect that the required power consumption is extremely small. In the case of cyclic memory, the conditions are different.

In order to carry out the cyclic operation, the address arrives in the form of a binary code and is always added at regular intervals by one to the number represented by the binary code. On the memory side, there is an element that receives the binary code corresponding to each digit of the number, and the state of the receiving element changes according to the incoming code. The state of this receiving element is decoded into a position corresponding to the address and the information of the area specified by that address is read out.
Or write. With this structure, each time the code giving the address changes, some of the elements receiving it operate and change their state.

Considering these numbers, the natural binary numbers are shown in Figure 1. For example, if an address is represented by a 3-digit natural binary number made up of 3 bits, and the address increases by 1 at regular intervals, when the number changes from 1 to 2, the binary number will be in the 1st digit. and the second two digits (2 bits) change, and when changing from 7 (111) to O (000), all (3) bits change.

In other words, when the address data changes, the address
One to three data receiving elements operate simultaneously. When a plurality of cyclic memories operate in parallel at the same time, such address/data inversions occur all at once at a specific address. When using a MOS C as a memory element, there is an imbalance in which the power consumption of the address driver increases intensively at the time of such address/data inversion, and the power consumption is low at other address times. This causes the load on the power supply to fluctuate. This complicates the design of the power supply system of the device, and intensive power consumption at a particular address may generate large pulse-like noise in the power supply route, which may impair the stability of the device. As described above, when the MOS C memory is used as a cyclic memory, the conventional control method has the disadvantage that it is difficult to take advantage of the inherent advantage of the element in operating at low power.

In the case of cyclic memory address control, the present invention
The purpose is to avoid intensive consumption of power at a specific address, reduce power consumption on average, and improve device operability.

Furthermore, according to the present invention, interfacing with a processing device is relatively easy, and a cyclic memory can be easily constructed using a MOS IC. According to the present invention, a cyclic memory is provided, which receives address data whose addresses change cyclically in a fixed order and with a fixed cycle, and reads or writes to the address,
The above object has been achieved by providing the address data in the form of alternating binary codes to the cyclic memory for control.

The invention will now be explained with reference to the drawings.

FIG. 2 shows an example of an alternating binary code, or Gray code, used as address data in the present invention.

Although the figure shows the case of 3 bits, it is clear from the figure that when two adjacent numbers are compared, only one data bit differs. Therefore, if this is given as address data to the sitter memory one after another at regular intervals, only one of the address/data receiving elements will be inverted, and the power consumption in this case is that only one element will always be inverted. Only the power required for inversion is equalized, and power consumption is not concentrated due to address data. The relationship between the natural binary code and the alternating binary code is relatively simple, and can be expressed as follows if the data bits of the natural and alternating binary codes are respectively Ai and bi (i represents a digit).

However, 1 is an exclusive OR. Police box 2 from natural binary numbers
Conversion into a base number can be implemented using a logic circuit as shown in FIG. 3 according to the above formula, and of course, if there are many digits, such a circuit can be created for each digit. In the figure, Al and A2 are AND circuits, 0 is an OR circuit, and Nl
, N2 indicates negation. 4 through 7 are block diagrams of embodiments of the present invention.

In FIG. 4, when there is write data at each address of the cyclic memory 20 from a processing device (not shown), the cyclic memory 20 has an address line 52 from the processing device, an address selector 30, and a natural alternating binary code. The corresponding address is sent by the converter 60 and data is sent from the processing device through the data line 54. On the other hand, since a write command is given to the write command line 56 from the processing device, a write pulse is sent to the write line 57. When the signal arrives, a signal appears at the output of the AND circuit 40, which causes data to be written into the cyclic memory 20.

The data written in the cyclic memory 20 is
Output line 51 of natural binary code generation circuit 11. The data is cyclically read out via the address selector 30 and the alternating binary code converter 60, and outputted via the readout output line 53 to the readout data utilization device 10, such as a highway switch.

The cyclic memory 20 may also be cyclically written to by the read data utilization device 10 via an input line 58, or may be read data irregularly by the processing device via a read line 55 to the processing device. .
In any case, normally the natural binary code generating circuit 11 performs a cyclic read or write operation to the read data utilization device 10.

Here, the address data sources for the cyclic memory 20 include the natural binary code generation circuit 11 and the address line 52 from the processing device that sends address data in the form of natural binary codes. All data input to the cyclic memory 20 are converted into alternating binary codes by a code converter 30 and provided as address inputs to the cyclic memory 20. Therefore, the address bit of cyclic memory 20 always changes by only one bit, and cyclic memory 20 operates under this condition. FIG. 5 is a block diagram of another embodiment of the invention. The numbers in the figures correspond to those in FIG. In this embodiment, an alternating binary code generating circuit 12 is provided in place of the natural binary code generating circuit, and the address data in the natural binary code given from the processing device via the address line 52 is sent to the natural alternating binary code converter. 60, and enters the address selector 30 in the form of an alternating binary code, and then enters the cyclic memory 20, and is otherwise similar to the one shown in FIG. 4, and its operation is also the same.

FIG. 6 is a block diagram of yet another embodiment of the present invention.

In the figure, the numbers refer to the same numbers as in FIG. 4. In this embodiment, when writing to or reading from the cyclic memory 20 from the processing device, data from the output line 51 of the natural binary code address/data generation circuit 11 and natural 2 data coming from the processing device via the address line 52 are used. The match detection circuit 70 monitors the address data in the decimal code, and when a match occurs, a signal is output to the output line 80, so the AND circuit 40 is operated, and the read/write operation from the processing device to the cyclic memory 20 is performed. Cycling
Queue control is performed in accordance with the operation of the memory 20. address·
The cyclic operation of the data generating circuit 11 to the utilization device 10 is the same as in the embodiment shown in FIG. FIG. 7 is a block diagram of yet another embodiment of the present invention.

In the figures, the numbers represent the same things as in FIGS. 4 and 6. In this example as well, the access from the processing device to the cyclic memory 20 is controlled by waiting, which is the same as in the example shown in FIG. 6, but unlike the example shown in FIG. The address data is generated in the form of a binary code, and therefore, the address data sent from the processing device in the form of a natural binary code via the address line 52 is first converted into a natural binary code. The data is converted into an alternating binary code by an alternating binary code converter 60, and a coincidence detecting circuit 70 detects a coincidence with the output data of the address/data generating circuit 12 for control. The subsequent cyclic operations for the control and utilization device 10 are as follows.
This is similar to the embodiment shown in the figure.

In the present invention, as described above, the address data input to the cyclic memory is an alternating binary code. When cyclic memory operates with alternating binary codes,
As mentioned above, the address/data bit always changes by one bit, and the number thereof is constant. Therefore,
When a large number of such cyclic memories are installed in parallel, the number of address, data, and bits that change at each point in time for each memory is always constant. In a cyclic memory using such an element, power consumption is always kept constant at the lowest level, and a cyclic memory can be constructed which is extremely superior in terms of power consumption and noise generation. Furthermore, in processing devices, natural binary codes are normally used, but if the cyclic memory control method of the present invention is to be introduced, a code converter is required to convert the natural binary codes into alternating binary codes. , this is the third
Since it can be easily configured as shown in the figure, a conventional interface is possible, and furthermore, the cyclic memory (indicated by 20 in Figures 4 to 7) is a natural binary code. It also has the advantage that conventional products designed for this purpose can be used as they are.

[Brief explanation of the drawing]

Figure 1 shows a 3-bit natural binary code, Figure 2 shows an alternating binary code, Figure 3 shows a logic circuit for converting a natural binary code into an alternating binary code, and Figure 4 shows a logic circuit for converting a natural binary code into an alternating binary code. Figures 5 and 6
7 and 7 are block diagrams of different embodiments of the present invention. In the figure, 11 is a natural binary code address/data generation circuit, 12 is an alternating binary code address/data generation circuit, 20 is a cyclic memory, and 60 is a natural/alternating binary code.
It is a decimal code converter.

Claims (1)

[Claims] 1. A cyclic memory that receives address data whose addresses change cyclically in a fixed order and with a fixed cycle, and reads or writes to the address, and converts the address data in the form of an alternating binary code, A cyclic memory control method characterized in that the cyclic memory is controlled by being applied to the cyclic memory.