JPS5922406B2 - tuning device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generates a tuning voltage according to digital information preset in a memory, and tunes to a desired channel in a so-called varactor tuner using a varactor (variable capacitance diode) as a tuning element. This is related to the tuning method that was used.

When electronically performing tuning switching operations in television receivers, radio receivers, etc., a DC voltage set for each tuning frequency is generated, and this DC voltage is used to control a varactor, which is a tuning element. However, the problem with this tuning switching operation is that it is necessary to faithfully apply the DC voltage set for each tuning frequency to the tuning element.

The present invention has been made to solve the above problems, and embodiments thereof will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a tuning device employing the tuning method of the present invention, in which a fundamental frequency oscillator 1 generates a fundamental frequency f.

oscillate. For example, the fundamental frequency f. =2,048
Considering KHz, this fundamental frequency f.

is frequency-divided by 1/211 by basic frequency dividers X2 to X12 to obtain a first frequency-divided signal f1.

Fundamental frequency f. = 2.048KHz, the frequency division signal f
1=lKH2.

This frequency divided signal f1 is used as a trigger signal for the monostable multi-bi break 2 and a read timing signal for the memory 3.

The frequency divided signal f1 is subjected to duck frequency division by the fine adjustment frequency divider X1,
Furthermore, there is a frequency divider X for removing jitter.

, ~Xo2 to become the 20th frequency-divided signal f2.

This frequency-divided signal f2 has a fundamental frequency f.

When is 2.048KHz, it becomes 125Hz.

Fundamental frequency f.

, the first frequency-divided signal f1, the second local signal f2, and the output signals f and I of the monostable multivibrator 2, respectively, are shown in FIG.

The pulse width of the output signal f1' of the monostable multivibrator 2 can be adjusted by a variable resistor 4.

During the preset period, the pulse width of the output signal f1' is converted into digital information and written into the memory 3, and a corresponding potential is applied to the varactor.

Next, a method of converting the pulse width of the output signal f1' into digital information will be described.

Basically, the fundamental frequency f comes while the output signal f1' is present.

The width of the pulse is converted into a digital signal by counting the number of .

The output signal f1' of the monostable multi-bi break 2 is applied to one input of the AND gate 5, and the fundamental frequency f is applied to the other input.

and write counter W for jitter removal.

1 input, and the fundamental frequency f while the output signal f1' is coming.

is input to the counter Wo1 and the fundamental frequency f.

The number of pulses is counted. This count is the frequency-divided signal f2 after passing through the preset switch 6, and is written into the write counter W for removing jitter.

This continues until 1°Wo2 and memory write counters W1 to W12 are reset at the same time.

The contents of the counters W1 to W, 2 before being reset are written to the memory 3, and 8 output signals f1' (23) are generated during the period from reset to reset.

Therefore, the counter W.

1. The fundamental frequency f that should originally be counted is in Wo2 and counters W1 to W12.

8 times the number of pulses will be counted.

However, the counter W.

1. The contents of Wo2 are not stored in memory 3 and are ignored.
After all, the fundamental frequency f that should originally be counted by the counters W1 to W12.

Twice the number of pulses will be counted.

Moreover, the number of pulses counted is the average of four pulses.

The number of times of this averaging is determined by the frequency divider X for removing jitter.

1. Xo2 frequency division ratio and write counter W for jitter removal
.

1. It is easy to understand that it can be arbitrarily selected by changing the count number of Wo2.

This averaging method means that even if the pulse width of the output signal f1' of the monostable multivibrator 2 varies slightly each time, that is, even if there is jitter, the average of these pulse widths is taken. However, the write operation to the memory 3 is made stable.

The address of the memory 3 corresponding to the channel is selected by the channel selection switch 7, and the contents of the counters W1 to W12 are written to the memory 3 at the timing of the frequency division signal f2.

FIG. 3 shows an example in which a numerical value of 3.5 is written into the memory 3 in order to explain the operation of the write counters W1 to W12.

In this example, the output signal f of the monostable multivibrator 2,
The case where the pulse width of ' is varied as 3.4, 3, 2, 4, 5, and 4.3 depending on the number of clock pulses of the fundamental frequency f1 is shown.

Even with this much variation, by using the averaging method, the frequency divider f2 can be used as a counter W.

1. Wo2. The final values before W1 to W12 are reset are (Wl, W2. W3. W, ...W12
)=(1°1.1,0.....0).

The weight of each counter output is Wl: 2-1 #W2:
2°, W3:21. W4:22,...W12
: 210.

The final value of the counter in the example of Figure 3 is IX2 'XlX
2°+1X21+0×22+...0X210=
3.5, this final value is written into the memory 3 at the timing of the frequency division signal f2.

Monostable multivibrator 2 written in this way
The method for reading out the output pulse width information will be described below.

As in the case of writing, the address of the memory 3 is selected by the channel selection switch 7, and the contents of the memory 3 are read out to the fine adjustment memory read register R1 and the memory read counters R2 to R12 at the timing of the frequency division signal f1.

Set the RS flip-flop Q1 with the divided signal f1,
Set the output to logic "1", open the AND gate 8, and set the fundamental frequency f.

is placed in the memory read counters R2 to R12 and counted down.

When the counters R2 to R12 all reach logic 60'', the output of NOR gate 9 becomes logic 1, resetting the RS flip-flop Q1.

When the output of the RS flip-flop Q1 becomes logic "0", the AND gate 8 closes and stops the countdown operation of the counters R2 to R12.

R8B The output of the flip-flop Q1 is shifted to the shift register Q2.
and the fundamental frequency f as the clock signal.

is used to create a signal delayed by l clocks of the RS flip-flop Q1.

The output of this shift register Q2 is input to an AND gate 14 and also to an AND gate 10 via an inverter 15.

In addition, the T-flip float S inverts the output polarity every time the frequency division signal f1 arrives, and if the output polarity is
One clock pulse is output from the AND gate 10 at lsQ2 timing.

Expressed as a logical formula, it becomes (R1・Ql・Wataru,・S).

The timing chart explaining the above read operation is shown in the fourth section.
As shown in the figure.

This example shows a case where information 3.5 is read from the memory in the same way as when writing.

The output of the OR gate 11 is Ql・Q2+R1・Ql・ζ
2.S) Generate a signal.

In Figure 4 (Ql・P2+R1・Ql・ζ2・S)
The signal has a fundamental frequency f.

If the number of clock pulses is 3.4, 3.4, etc., and the average value is taken, an output of 3.5 will be obtained.

(Ql.Q2+R1.Q1'...times 2.S) The signal enters the low-pass filter 13 via the voltage level converter 12, generates a voltage corresponding to the output pulse width, and applies this potential to the varactor of the varactor tuner.

Strictly speaking, the output potential of the low-pass filter 13 depends not on the output pulse width of the OR gate 11 but on the duty cycle.

In this system, the fundamental frequency f of the fundamental frequency oscillator 1.

Even if the output signal of the OR gate 11 changes, the duty cycle of the output signal of the OR gate 11 does not change.

Therefore, it has the great advantage that the voltage applied to the varactor does not fluctuate.

The above is the configuration and operation of a tuning device that employs the tuning method of the present invention.The features of this device can be summarized as follows: (1) Even if the oscillation frequency of the fundamental frequency oscillator changes, the duty cycle of the output signal changes. The output varactor is therefore unaffected by the applied voltage.

(2) Regardless of the number of channels selected, the only adjustment part for presetting information in the memory is turning on the preset switch and adjusting the variable resistor to adjust the output pulse width of the monostable multivibrator.

When the adjustment of the variable resistor is completed, the preset switch is returned to the OFF state and the write operation to the memory is stopped.

(3) Since the pulse width of the monostable multivibrator is adjusted and preset is performed, conversion to a digital quantity to be stored in memory is facilitated.

(4) Even if the pulse width fluctuates each time due to jitter in a monostable multi-bibreak, it is stabilized by the averaging method.

(5) Even if a fraction (in the example, 0.5 of 3.5) occurs in the digital signal obtained by the above-mentioned averaging method, non-linearity of the active elements constituting the DA converter to be applied to the varactor etc. can be ignored.

This is used as a means to convert the voltage applied to the varactor corresponding to this fraction into the voltage applied to the varactor (M pips) (N>
Add pulse M).

However, it is desirable to add at most one bit to each cycle.

These output pulses enter a low-pass filter via a high-voltage voltage level converter to generate a DC voltage to be applied to the varactor.

becomes.

[Brief explanation of drawings]

Fig. 1 is an electrical wiring diagram of a tuning device employing the tuning method of the present invention, Fig. 2 is a waveform diagram showing the phase relationship between the fundamental frequency, the 11th and 2nd frequency divided signals, and the output signal, and Fig. 3 is A waveform diagram showing the phase relationship between the 11th and 20th frequency divided signals, the output signal, and each input/output signal of the jitter removal write counter and the memory write counter, FIG. 4 is a memory read register for fine adjustment,
FIG. 3 is a waveform diagram showing the interrelationship of output signals of a memory readout counter, an RS flip-flop, a shift register, and a T flip-flop. 1 is a fundamental frequency oscillator, 2 is a monostable multivibrator, 3 is a memory, 4 is a variable resistor, 6 is a preset switch, 13 is a low-pass filter, W1 to W, 2 is a memory write counter, R2-R12 is a memo, The read counters are shown respectively.

Claims (1)

[Claims] 1. The fundamental frequency obtained by the fundamental frequency oscillator is divided into a trigger signal and a memory continuous output timing signal for the monostable multivibrator, and further divided into a memory write timing signal at the time of presetting, and The output pulse width can be arbitrarily varied using a variable resistor, and the basic frequency is set as a memory write timing signal at the time of count 1 preset using a jitter removal counter and a memory write counter according to the output pulse of the monostable multivibrator. Based on the continuous output timing signal, the counted contents of the memory write counter are written to the memory, and the digital information written to the memory is divided into a memory continuous output counter and a memory continuous output register for fine adjustment and sequentially output based on the continuous output timing signal. The content of the continuous output counter is counted down according to the previous fundamental frequency, and the content is generated by the countdown output of the continuous output counter, the continuous output timing signal, the reference frequency signal, and the output of the fine adjustment memory read register. Based on the logical output signal, a DC pulse is generated with a constant period and a pulse width corresponding to the digital information, and the repeated pulse is applied to a varactor tuner through a voltage level converter and a low-pass filter. A method of tuning a varactor tuner characterized by deriving a tuning voltage.