JPS5940325B2 - Pulse width adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width adjustment device suitable for use in, for example, a television receiver.

Generally, in television receivers that perform electronic channel selection,
To vary the local oscillation output for tuning, there is a method of tuning by applying a DC voltage to a variable capacitance diode.

In this method, the tuning voltage is set to a different value for each cycle, but in order to set this tuning voltage, the pulse width of the output pulse of the monostable multi-bibreak is varied by varying the resistor or capacitor. Generates voltage according to duty.

In this case, the difference from mechanical type is that to generate the desired voltage, a digital signal (replaced with a digital signal) according to the corresponding pulse width, and the digital signal is stored in memory.
When needed, the digital signal must be recalled from memory to generate voltage and obtain tuning.

Therefore, a write operation (or preset) is first required to store the digital value in the memory, and then a read operation is also required to recall the necessary data from the memory.

In addition, in order to perform the desired writing and reading operations, a changeover switch is required, and when writing, after operating the switch, adjust the volume to the desired voltage, and then use the changeover switch again to switch to the readout side. This requires a lot of effort and trouble when writing.

Furthermore, if this channel selection section is made into an IC, the wires of the switch other than the wires connected to the monostable multi-vibration loop are 1.
~2 IC pins are required, and as a result, the number of IC pins must be increased, resulting in an increase in cost.

Furthermore, the number of wires connecting the operation panel and the control circuit increases, making the configuration complex, and even with a switch-equipped volume control, the increase in lead wires and IC pins cannot be prevented.

This invention eliminates the above-mentioned drawbacks of the conventional technology, and eliminates the need for a read/write selector switch. Also, during a write operation, the three operations of switch switching, voltage adjustment, and switch switching can be completed with one voltage adjustment operation. To provide an inexpensive pulse width adjusting device with a simple configuration that eliminates a changeover switch and saves lead wires and IC pins.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The pulse width adjustment device of the present invention is configured to perform a switching operation and a channel selection operation in accordance with the original pulse width modulation according to the output pulse width, and is configured as shown in FIG. There is.

That is, the input terminal 1 is connected to a monostable multivib brake 2 and a pulse generation circuit 3 consisting of, for example, a monostable multivib router.
It is connected to the.

The output side of the monostable multi-bi break 2 is connected to the OR gate 4c.

Further, the pulse generating circuit 3 is connected to a Nandt gate 6 via an inverter 5 (which is also connected to the OR gate 4).

The output side of this OR gate 4 is connected to 80 NAND gates constituting the latch circuit 7.

Further, the output side of the Nandts gate 6 is connected to a Nandts gate 9 constituting the latch circuit 1.

The output side of this Nandt gate 9 is connected to the output terminal 10 and the input side of the Nandt gate 8, and the output side of this Nandt gate 8 is connected to the input side of the Nandt gate 9. There is.

In addition, the television receiver (if this is used, output terminal 1)
0 is connected to a memory (not shown).

Now, in the above-mentioned pulse width adjustment device ζ, the monostable multi-bi break 2 has a variable capacitor attached to the external variable resistor so that the time constant can be changed, and the pulse generation circuit 3 has a constant time constant and generates pulses with a constant pulse width and period.

Further, the latch circuit γ performs set/reset operations, and its output changes the switch, that is, opens and closes the gate.

Now, if the device (this power supply is turned on), the monostable multi-bi break 2 and the pulse generation circuit 3 are always supplied with a constant cycle trigger pulse Cpt (shown in Fig. 2a) via the input terminal 1.
is supplied.

In this case, the output pulse width tw (see Figure 2) of the pulse generation circuit 3 with a constant time constant is set to be small, but the output of the pulse generation circuit 3 is
, but the signal CI) iM that passed through Impark 5 is the second
As shown in the figure, it is supplied to the Nandro game and the OR gate 4.

On the other hand, the output of the monostable multi-by break 2 is supplied to the Nandt gate 6 and the OR-gate 4 &; if the output M1 of the monostable multi-by break 2 is smaller than the number tw as shown in FIG. 2 CIC, the signal CI ) M and out M1
The output S of the Nando Gate is always ``1'' as shown in Figure 2d, and the output R that has passed through the gate 4 has a waveform as shown in Figure 2ec. .

Each output S and R is a tend gate of the latch circuit 7, respectively.
) 9.8, the latch circuit γ is always reset to O, so the output appearing at the output terminal 10 remains at "O".

By connecting this output to an R/W gate of a memory (not shown), the memory is placed in a read state.

At this time, the output of the monostable multivibrator 2 has no influence anywhere.

By operating the external variable resistor of the monostable multi-bi break 2, the width of the output pulse can be changed to t as shown in Figure 2 f.
When expanded beyond w, the output S of the Nant gate 6 of the signal 'CpM and the output M2 has a waveform as shown in FIG. 2g.

At this time, the output R of the OR gate 4 becomes "1" as shown in the second diagram.

Therefore, the latch circuit 7 continues to be set, and the output is always "1".
"become.

At this time, it is in the writing state, so a voltage corresponding to the output of the monostable multivib router 2 is generated, and at the same time it is applied to the tuner, the value converted to a digital value can also be input to the memory.

The pulse width of the output of monostable multivib router 2 is set to t again.
If it is made smaller than 'w, the set output is "1" and a reset pulse is generated, which inverts the latch circuit 7 and returns to the "0" state (returns).

In this way, reading and writing modes can be selected with a single variable resistor, and pulse widths (and thus voltages) of the monostable multi-by-break 2 and pulse generating circuit 3 can be changed in accordance with the variable resistor.

In addition, in FIG. 1, OR gate 4. Inverter 5. Although the outputs S and R are obtained using a logic circuit using a Nant gate 6, the pulse width of the signal CPM is not limited to these circuits.

When the pulse width is larger than the pulse width of
'', the output R outputs a signal having a pulse width corresponding to the period from the trailing edge of the pulse M1 to the trailing edge of the signal CpM, and the pulse width of the signal CI)M' is the same as that of the pulse M2.
when the pulse width of the output S is smaller than the pulse width of the signal CpM
Any logic circuit may be used as long as it outputs a signal having a pulse width corresponding to the period from the trailing edge to the trailing edge of the pulse M2, and the output R is always "1".

In addition, the pulse width twI of the output CI)M corresponds to the switching operation according to the rotation angle of the variable resistor.

The ratio of "0" changes.

Further, if the output CpM is obtained from another circuit, the pulse generation circuit 3 is not necessary.

Since the pulse width adjusting device of the present invention is constructed as described above and shown in the drawings, the switching operation can be performed with a single external variable resistor without using a changeover switch as in the prior art.

In other words, there is no need for a read/write selector switch, and when writing, the three operations of switch switching, electronic adjustment, and switch switching can be done with one voltage adjustment operation, so lead wires and IC pins can be saved and the configuration is simple. And it's cheap.

Of course, when a television receiver is used, it is possible to perform channel selection without impairing the original function of the monostable multi-by-break, which is convenient and saves a lot of trouble.

Note that the pulse generating circuit 3 in the above embodiment is not limited to a monostable multivibration circuit, but may be any circuit as long as it generates a pulse with a constant pulse width and period.

As explained above, according to the present invention, it is possible to provide a pulse width adjustment device with great practical value.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a pulse width adjustment device according to an embodiment of the present invention, and FIGS. 2a to 2h are signal waveform diagrams showing various signals in the pulse width adjustment device of FIG. 2... Monostable multivibration roof, 3...
...Pulse width generation circuit, 4...OR gate, 5
...Inverter, 6...Nand gate, 7...Latch circuit, 8.9...
Nandgate.

Claims (1)

[Claims] 1. A first pulse generating circuit which is supplied with a trigger pulse of a constant period, generates a first pulse of the same period as the trigger pulse, and has means for varying the pulse width of the first pulse. , a second pulse synchronized with the trigger pulse and having a constant pulse width;
a second pulse generation circuit that generates a pulse; and pulses from the first pulse generation circuit and the second pulse generation circuit are respectively supplied as manual pulses, and a first output signal and a second output signal. , wherein when the pulse width of the first pulse is smaller than the pulse width of the second pulse, in the period from the trailing edge of the first pulse to the trailing edge of the second pulse. outputting a first output signal having a corresponding pulse width and a second output signal always having a constant level; when the pulse width of the first pulse is larger than the pulse width of the second pulse; a logic circuit that outputs a second output signal having a pulse width corresponding to the period from the trailing edge of the second pulse to the trailing edge of the first pulse, and always outputs the first output signal at a constant level; A pulse width adjustment device comprising a latch circuit that is supplied with a first output signal and a second output signal from the logic circuit and performs a set/reset operation.