JPS5922437B2 - Signal detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal amplitude detection circuit, and more particularly to a portion of the output logic circuit of a digital pushbutton receiver.

Conventionally, digital push button receiver (hereinafter referred to as PBREC)
In this system, a method as shown in FIG. 1 is used as a method of detecting the output amplitude of a band-pass filter provided for each PB signal frequency.

, (For simplicity, the following explanation will be based on one wave of the PB signal.) In the figure, 1 is a digital filter with band-pass characteristics, and the output is the one wave of the PB signal that is demultiplexed and output. be done. This output is full-wave rectified by a digital full-wave rectifier circuit 2, and then a DC component is extracted by a digital filter 3 having low-pass characteristics. This DC component is compared with the output of the memory circuit 4 that stores a predetermined threshold value by the digital comparator 5, and the result of the comparison with the threshold value of the output signal amplitude of the bandpass filter is finally output to the terminal. 6. As explained above, in the prior art, a digital low-pass filter was used to detect the amplitude of the output signal of the band-pass filter, but as is well known, the digital filter has a complicated configuration, and as a total of 5 filters. It had the disadvantage that it required a large amount of hardware and was not economical. The purpose of the present invention is to
To detect the output amplitude of a band-pass filter, it is possible to do this using a simple logic circuit without using a digital low-pass filter, and to obtain an economical signal detection method with a small amount of hardware. be.

In the present invention, in order to detect the output signal amplitude of the bandpass filter, the signal is first subjected to full-wave rectification.

The result of this full-wave rectification is compared with a predetermined threshold value, that is, a DC level, and converted into a (1, 0) logic signal. This logic signal may be thought of as a one-pit PCM code corresponding to whether the instantaneous amplitude of the signal exceeds the threshold value. This logic signal is logically accumulated for a certain period of time. Logical accumulation is 0+O=0,1+0=1,0+
1=1, 1+1=1. This cumulative result is reset and sampled at the above-mentioned fixed time intervals, and based on the sampled results, if it is 111I, it is determined that the input signal is greater than the threshold value, and if it is 101, it is determined that the input signal has not reached the threshold level. You can. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention. According to FIG. 2, the embodiment of the present invention has a bandpass filter input terminal 0, a digital filter 1, a digital full-wave rectifier circuit 2, a threshold value storage memory 4, a digital comparison circuit 5, an OR gate 7, a shift register 8, It is composed of AND gates 9 and 10, a signal detection output terminal 6, a sample signal input terminal 11, and the like. The operation of this circuit will be explained below. A PB signal separated into a single frequency by a digital filter 1 having bandpass characteristics is applied to a digital full-wave rectifier circuit 2, and the amplitude of the signal is converted to unipolar. This is the DC level from the threshold fault memory 4 and the digital comparator circuit 5.
The instantaneous samples are converted into 1-bit logic signals. Here, if the instantaneous amplitude exceeds the threshold value, it is 1111, otherwise it is 10W1. This result is latched into the shift register 8 via the OR gate 7. The output of the shift register 8 is fed back to one input of the OR gate 7, so that the logic 111 is accumulated. The fact that the instantaneous amplitude of the AC signal exceeds the threshold value t is recorded in the shift register 8.The result of this shift register is sampled at regular intervals via the AND gate 10 and sent to the output terminal 6. Obtain the desired output.As the system register 8 is resampled, it is also reset to prepare for the next accumulation.The above-mentioned fixed time must cover at least one period of the PB signal.For example, the maximum period signal 697
Considering the Hz, 2 milliseconds is sufficient. In the above explanation, the PB signal has been explained as having one frequency.

As is well known, the PB signal has multiple frequencies (eight waves). In this case, digital filter 1, digital full-wave rectifier circuit 2
, digital comparator circuit 5, etc. are used in time division multiplexing to perform calculations corresponding to each frequency. In addition, the shift register 8 is 8×N(
Needless to say, it is sufficient to use a shift register that is as long as the number of bits (N is the number of PBREC circuits). Note that output terminal 6
A series of timer processing is further performed using the detection results obtained for each frequency to obtain the PBREC output, but since it is not directly related to the present invention, its explanation will be omitted.

Figure 3 shows the output of 1 band filter 1 and 2 the output of full wave rectifier circuit 2.
An example of the operation of the output of 3, the logic output of comparator 5, the contents of 4 shift register 8, and the detection output of 5 is shown in a time chart.

1 and O are PAM representations, and 3, 0, and 5 are logical representations.

As explained above, in the present invention, when detecting the amplitude of a signal, a digital filter having low-pass characteristics is created by using a method of logical accumulation with reset of the logical signal after instantaneous amplitude comparison. It was deleted.

This makes the hardware configuration simple and provides an economical digital signal detection circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional digital signal detection method, FIG. 2 is a block diagram showing an embodiment of the digital signal detection method according to the present invention, and FIG. 3 is a block diagram showing an example of the operation of digital signal detection according to the present invention. This is a time chart. 1: Digital filter, 2: Digital full-wave rectifier circuit, 4: Threshold storage memory, 5: Digital comparison circuit,
7 rear gate, 8: shift register, 9, 10: AND gate.

Claims (1)

[Claims] 1. In a digital signal detection circuit that tests the magnitude of the amplitude of an alternating current signal separated into single frequency waves by means such as a digital filter, the instantaneous amplitude is compared through a comparison circuit that compares the single frequency signal with a direct current level. After converting into a logic signal, this logic signal is logically accumulated for a certain period of time, and the accumulation result is sampled at the same time as the above-mentioned periodic interval is reset, and the amplitude test result of the above-mentioned alternating current signal is determined based on the sample result. A signal detection method characterized in that it is configured to obtain a signal.