JPH0657072B2 - In-band SF signal detection circuit by digital signal processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, an S channel within each band from a communication channel received via a communication circuit of a frequency division multiplex system is received.
The present invention relates to a circuit for detecting an F signal, particularly an in-band SF (Single Frequency) signal detection circuit by digital signal processing.

Conventionally, in this kind of multi-channel signal transmission system, S that is used as a signal system for telephone exchange on the receiving side.
In order to detect the F signal, an independent signal converter is used for each channel, whereby only the SF signals mixed in the signals in the respective bands are separated in an analog manner. However, according to this method, as the number of channels increases, the number of signal converters used increases in proportion to the increase in the number of channels. Then,
There is a drawback that the input signal pulse cannot be detected accurately.

Therefore, an object of the present invention is to improve the economical efficiency by eliminating the drawbacks of the prior art constituted by an analog circuit, utilizing the signal processing technology by a digital filter, and processing a large number of channels in a time division manner. Another object of the present invention is to provide an in-band SF signal detection circuit that can accurately detect an input pulse even if the level of the digital signal pulse changes.

According to the present invention, a digital signal of two's complement display is inputted and a digital band pass type digital filter for digitally filtering the digital signal, and a band elimination type digital filter for inputting the digital signal and digitally filtering the digital signal are also inputted. A filter, a first absolute value conversion circuit that receives the output of the band-pass digital filter and outputs its absolute value, and a second absolute value conversion circuit that receives the output of the band-elimination digital filter and outputs its absolute value A value conversion circuit, a first time constant, a first integration circuit that integrates the output of the first absolute value conversion circuit, and a second time constant that is larger than the first time constant. A second integration circuit for integrating the output of the second absolute value conversion circuit and a level comparison circuit for comparing the output of the second integration circuit with the output of the first integration circuit as a reference. For example, it was characterized by obtaining a band single-frequency signal from an output of said Reneru comparison circuit, the in-band SF signal detecting circuit according to the digital signal processing is obtained.

By the way, basically, it is possible to compare the powers of the SF signal component and other components and to judge that the SF signal exists when the signal component is higher by about 10 dB (the guard ratio is said to be 10 dB). it can. However, when this method is implemented digitally, since a dial pulse is also treated as a signal, the pulse must be detected without distortion even when the input level fluctuates. In consideration of this point, the present invention takes advantage of the characteristics that the responses of the band-elimination type digital filter and the band-pass type digital filter are of the differential type and the integral type, respectively, and when detecting the power of the signal, the time constant is The above conditions are satisfied by placing a significantly different integrating circuit.

Next, an in-band SF signal detection circuit according to the present invention will be described with reference to the drawings with reference to embodiments.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, the input terminal 1
Audio signals of a plurality of channels which are digitized by a two's complement display are given in a time division format via an A / D conversion circuit (not shown). In this case, in-band SF signals are mixed for each channel. The band-pass digital filter 2 receives the above digital input signal and extracts only the frequency component corresponding to the selected SF signal. The band elimination type digital filter 3 also receives the above digital input signal and extracts frequency components other than the SF signal. Referring to FIG. 2 showing operation waveforms of each element, FIG. (A) shows the waveform of the digital input signal a, and FIG. (B) shows the waveform of the output b of the digital filter 2.
Then, FIG. 6 (c) shows the waveform of the output c of the digital filter 3, respectively. The absolute value conversion circuit 4 receives the output b of the digital filter 2, converts the digital value into an absolute value, and outputs it as a signal d. The other absolute value conversion circuit 5 receives the output c of the digital filter 3 and
The digital value is converted into an absolute value and output as a signal e. Here, the signals b and d are respectively shown in FIG. 2 (b).
As shown in waveforms (d) and (d), when a signal having a pass band frequency is applied to the band-pass digital filter 2, the signal rises and falls gently in order to show an integral response. On the contrary, when a signal having a frequency in the stop band is applied to the band-elimination type digital filter 3, a response appears only at each of the rising and falling edges of the signal due to the differential operation, and the signals c and e are shown in FIG.
The waveforms are as shown in (c) and (e). The integral response of the band-pass digital filter and the differential response of the band-elimination digital filter are functions originally possessed by the band-pass and band-elimination digital filters. It does not have a special configuration for realizing the response.

The integrator circuit 6 selects a specific number relatively short, and the integrator circuit 6 converts the signal d into the DC signal f ₁ in consideration of the slow response. The other integrating circuit 7 has a specific number set to be considerably long, and the integrating circuit 7 converts the signal e into a signal f ₂ having a DC waveform with a considerably slow response. By such a treatment by the integrating circuit, the signals f ₁ and f ₂ have a waveform as shown in FIG. 2 (f).
These signals f ₁ and f ₂ are respectively applied to the level comparison circuit 8, and the level of the signal f ₁ is compared with the level of the signal f ₂ as a reference, and a signal g as shown in FIG. 2 (g) is obtained. It is led out to the output terminal 9 as an in-band SF signal.

Referring to the waveforms of the signals a and g, no matter how the level of the digital input signal applied to the input terminal 1 changes,
As long as the signal width Δt is constant, the pulse width Δt ¹ of the signal g remains constant. In FIG. 6F, the time length from the appearance of the response to the detection of the pulse t ₁ is different from the time t ₂ from the detection of the trailing of the pulse after the falling edge to the time t ₂ . As a result, although Δt and Δt ¹ do not match, the difference t ₁ −t ₂ is always constant and can be easily calculated by simulation. Therefore, it is possible to restore the signal width of Δt by correcting Δt ^1. It is possible. Further, since it is not judged that it is a signal for t ₁ time after the rise of the pulse, even if the voice signal happens to contain the same frequency component as the signal, it is not regarded as a signal if it is shorter than t ₁ . As a practical matter, it is rare that a single frequency component continues for several msec or more in human voice, so t ₁
If is designed to be about 5 msec, it is possible to prevent erroneous recognition of signals. In this way, the in-band SF signal is detected from the digital signals sequentially applied to the input terminals for each channel and obtained at the output side.

As is clear from the above description, according to the present invention, by effectively utilizing the digital signal processing function by time division, a large number of channels can be processed in common, which results in a great reduction in hardware. Of course, the effect that the input pulse can be accurately detected even if the level of the input digital signal pulse changes can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention,
FIGS. 2 (a) to 2 (g) are waveform diagrams for explaining the operation in the embodiment of FIG. In the figure, 2 is a band pass digital filter, 3 is a band elimination digital filter, 4 and 5 are absolute value conversion circuits, 6 and 7 are integration circuits, and 8 is a comparison circuit.

Claims (1)

[Claims] 1. A two's complement display digital signal is input,
A digital band pass type digital filter for filtering this digitally, a band elimination type digital filter for similarly inputting the digital signal and digitally filtering this, and an absolute value for receiving the output of the band pass type digital filter. A first absolute value conversion circuit for outputting a value, a second absolute value conversion circuit for receiving the output of the band elimination type digital filter and outputting the absolute value thereof, a first time constant, and A first integrator circuit that integrates the output of the first absolute value conversion circuit, and a second integration circuit that has a second time constant larger than the first time constant and that integrates the output of the second absolute value conversion circuit Of the second integrating circuit and a level comparing circuit for comparing the output of the second integrating circuit with the output of the first integrating circuit as a reference, and an in-band single frequency signal from the output of the level comparing circuit. It was characterized by obtaining, in-band SF signal detecting circuit according to the digital signal processing.