JPS5922968B2 - constant current circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses MOS transistors to realize a constant current circuit that has a relatively simple configuration but has extremely good stability of output current against changes in supply voltage. be.

As is well known, MOS transistors are originally constant current devices, and if the voltage between the gate and source is kept constant, the drain current will remain constant regardless of fluctuations in the supply voltage. However, there is no suitable method to keep the voltage between the gate and source constant, and if a constant current circuit is configured using enhancement type MOS transistors, the circuit becomes complicated, and if the configuration is simplified, stability deteriorates. There were many problems.

The present invention provides a constant current circuit that skillfully utilizes the extremely high impedance between the gate and source of a MOS transistor and the fact that the drain current changes depending on the voltage between the gate and source.

FIG. 1 shows a circuit connection diagram of a constant current circuit in an embodiment of the present invention.
The gate of an N-channel enhancement type MOS transistor 2 is connected to the drain of the OS transistor 1, a resistor 3 is connected between the gate and drain of the MOS transistor 1, and both gates are connected to a positive power supply terminal 5 through a resistor 4. The source of the MOS transistor 1 and the source of the MOS transistor 2 are connected to the negative power supply terminal 6, and the drain of the MOS transistor 2 is connected to the output terminal □. An external load resistor 8 is connected between the terminals 5 and 5.

Now, in the constant current circuit shown in FIG. can be kept constant regardless of fluctuations in the supply voltage.

By the way, Figure 2 shows the positive side power supply when the internal transistor of the analog switch CMOSIC, MSM-4016 (manufactured by Oki Electric Industry Co., Ltd.) is used as the MOS transistor 1, and the resistance value R4 of the resistor 4 is set to 100Ω. terminal 5
The supply voltage EI applied between the negative side power supply terminal 6
The drain of the MOS transistor 1 with respect to the change in
The change in the voltage EO between the sources is measured by changing the resistance value R3 of the resistor 3.

From FIG. 2, under these conditions, if the resistance value R3 of the resistor 3 is set to 2.2KΩ, the drain-source voltage E of the MOS transistor 1 can be maintained even when the supply voltage EI changes.
It can be seen that O is kept almost constant.

In addition, since the impedance between the gate and source of MOS transistor 2 can be considered to be almost infinite, the MOS transistor 2
Even if the gate and source of the MOS transistor 2 are connected between the drain and source of the transistor 1, the MOS
The state in which the voltage between the drain and source of the S transistor 1 is kept constant does not change at all. Therefore, in the circuit of FIG. By choosing the voltage, a constant current can be supplied to the load resistor 8 regardless of changes in the supply voltage.

By the way, the circuit configuration of the circuit shown in FIG. 1 except for the resistor 4 is as described in, for example, No. 3 of JP-A-51-102679.
It is shown in the figure and is known.

However, from the measured characteristic diagram of FIG. 2, it can be easily predicted that if the resistor 4 is removed, it will not be possible to obtain a stable output current over a wide power supply voltage range.

This situation can be explained using a mathematical formula as follows.

First, in the circuit shown in FIG. 1, the voltage between the gate and source of MOS transistor 1 is 1, the drain current is IDl, the transfer conductance is Grn, the voltage between the gate and source of MOS transistor 2 is G1, the power supply voltage is E1, and resistor 3 ，
When the resistance values of 4 are R3 and R4, respectively, VG=E
I-(R3+R4)IO...(1) is established,
δVO/AE can be considered as a stabilization index of the output current.

From equation (1), ▲υA In equation (8), μ is carrier mobility, ε0,
ε0x is the dielectric constant in vacuum, the dielectric constant of the gate oxide film, TOx is the thickness of the gate oxide film, and W and L are the gate width and gate length, respectively.

Now, if the value of R4 is set to zero in equation (7), then when resistor 4 is removed, the output current can only be stabilized within an extremely limited range of power supply voltage. .

On the other hand, the stabilization index of the circuit shown in Fig. 1 can be expressed by equation (7), and by selecting the value of Gm-R4 to be sufficiently larger than 1, the resistance value of resistor 3 can be resistance 4
By choosing a value sufficiently small compared to the resistance value of , even if Gm itself is a drain current of 1.

The output current can be stabilized over a wide range of power supply voltages, even if the The value of the current flowing through the load resistor 8 can be changed by keeping the ratio of the resistance values of the resistors 3 and 4 constant and changing the resistance value itself. It is also possible to connect the source to the negative power supply terminal 6 via a third resistor, and change the output current by changing the resistance value of the third resistor.

Now, FIG. 3 shows a circuit connection diagram of a constant current circuit in another embodiment of the present invention, in which the drain of the MOS transistor 2 is directly connected to the positive power supply terminal 5.

That is, while the constant current circuit in FIG. 1 is a three-terminal constant current circuit, the constant current circuit in FIG. 3 is a two-terminal constant current circuit.

Naturally, if the ratio of the resistance values of resistor 3 and resistor 4 is made the same as in the circuit of FIG. 1, the stability of the output current will deteriorate due to the unstable current flowing through resistor 3 and resistor 4.
Since the unstable current increases as the supply voltage EI increases, the current flowing between the positive power supply terminal 5 and the negative power supply terminal 6 also increases as the supply voltage EI increases.

However, as can be seen from Figure 2, when the resistance value R4 of resistor 4 is set to 100K0, the resistance value R4 of resistor 3 is
If the value of 3 is set to a value larger than 2.2KΩ, the MO
Between the drain and source of S transistor 1, that is, M
The voltage between the gate and source of the OS transistor 2 decreases as the supply voltage EI increases. Therefore, in the constant current circuit shown in FIG. 3, by appropriately selecting the ratio between the resistance value R3 and the resistance value R4, the supply voltage El increases and the current flowing through the resistor 4 and the resistor 3 increases. As a result, the current flowing between the positive power supply terminal 5 and the negative power supply terminal 6 can be made constant regardless of changes in the supply voltage El.

In the circuits of FIGS. 1 and 3, the resistors 3 and 4 do not need to be dedicated resistance elements (solid resistors, carbon resistors, etc.), but can be connected between the drain and source of a MOS transistor, etc. It is clear that it can also be substituted. As shown above, the constant current circuit of the present invention has a second MOS transistor connected to the drain of the first MOS transistor.
A first resistor is connected between the gate and drain of the first MOS transistor, and the gate is connected to one power supply terminal via a second resistor. The second M
Since it is applied to the gate of the OS transistor, it is possible to obtain extremely good stability against changes in the supply voltage of the output current with a relatively simple configuration, and it is very effective.

[Brief explanation of the drawing]

Fig. 1 is a circuit connection diagram of a constant current circuit in one embodiment of the present invention, Fig. 2 is an actual measurement characteristic diagram for explaining the operation of the circuit in Fig. 1, and Fig. 3 is another embodiment of the present invention. It is a constant current circuit connection diagram in . 1...First MOS transistor, 2...
...Second MOS transistor, 3...First resistor, 4...Second resistor, 5...Positive power supply terminal, 6...・Minus side power supply terminal, 7
...Output terminal.

Claims (1)

[Claims] 1. A gate of a second enhancement type MOS transistor is connected to the drain of the first enhancement type MOS transistor, a first resistor is connected between the gate and drain of the first enhancement type MOS transistor, and the gate is connected to the drain of the first enhancement type MOS transistor. The first and second
A constant current circuit, characterized in that the source of the second MOS transistor is connected to the other power supply terminal, and a constant current output is taken out from the drain of the second MOS transistor.