JPS5923111B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5923111B2 JPS5923111B2 JP52016714A JP1671477A JPS5923111B2 JP S5923111 B2 JPS5923111 B2 JP S5923111B2 JP 52016714 A JP52016714 A JP 52016714A JP 1671477 A JP1671477 A JP 1671477A JP S5923111 B2 JPS5923111 B2 JP S5923111B2
- Authority
- JP
- Japan
- Prior art keywords
- resin film
- layer
- film
- bonding
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/922—Bond pads being integral with underlying chip-level interconnections
- H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、保護膜或いは絶縁膜として樹脂皮膜を用い、
且つ、ボンディング・パッドを有してなる半導体装置の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention uses a resin film as a protective film or an insulating film,
The present invention also relates to improvements in semiconductor devices having bonding pads.
近年、保護膜或いは絶縁膜として例えばポリイミド等の
樹脂を用いることが行なわれている。In recent years, resins such as polyimide have been used as protective films or insulating films.
これは、従来多用されている燐硅酸ガラス（ＰＳＧ）膜
に於ける種々の欠点を解消することが狙いとなつている
。ところで、多くの半導体装置にはボンディング・パッ
ドが形成されていて、そこにリード線をボンディングす
ることが行なわれている。This is aimed at eliminating various drawbacks of phosphosilicate glass (PSG) films that have been widely used in the past. By the way, bonding pads are formed in many semiconductor devices, and lead wires are bonded to the bonding pads.
そして、そのボンディングには、通常、３〜７〔トン／
一〕の圧力が加えられる。従つて、前記の如く、樹脂皮
膜を用いた半導体装置に於いて、ボンディング・パッド
の圧力が印加される部分の直下に樹脂皮膜が在ると、そ
こで変形が発生し、その結果、パッドを形成している例
えばアルミニウム（Ａｌ）等の皮膜が下地から剥離する
事故が発生する。これは、多層の樹脂層を用いた多層配
線層を有する半導体装置では特に起り易い。本発明は、
樹脂皮膜を絶縁膜或いは保護膜として有する半導体装置
に強固なボンディング・パッドを形成し、ボンディング
時に圧力を加えても、半導体装置が損傷されないように
するものであり、以下これを詳細に説明する。The bonding process usually requires 3 to 7 tons/
1] pressure is applied. Therefore, as mentioned above, in a semiconductor device using a resin film, if the resin film is located directly under the pressure applied part of the bonding pad, deformation occurs there, and as a result, the pad is formed. For example, an accident may occur in which a film made of aluminum (Al) or the like peels off from the underlying layer. This is particularly likely to occur in semiconductor devices having multilayer wiring layers using multilayer resin layers. The present invention
A strong bonding pad is formed on a semiconductor device having a resin film as an insulating film or a protective film so that the semiconductor device will not be damaged even if pressure is applied during bonding.This will be explained in detail below.
図は本発明一実施例を表す半導体装置の要部切断側面図
である。The figure is a cutaway side view of essential parts of a semiconductor device representing an embodiment of the present invention.
図に於いて、１は半導体基板、２は二酸化シリコン（Ｓ
ｉＯ２）、燐硅酸ガラス（ＰＳＧ）、酸化アルミニウム
（Ａｌ２Ｏ３）等の絶縁膜、３は第１層樹脂皮膜、４は
例えばアルミニウム（Ａｌ）の第１層ボンディング・パ
ッド、５は第１層配線、６は第２層樹脂皮膜、７は第２
層ボンディング・パッド、８は第２層配線、９は第３層
ボンディング・パッドをそれぞれ示している。In the figure, 1 is a semiconductor substrate, 2 is silicon dioxide (S
iO2), phosphosilicate glass (PSG), aluminum oxide (Al2O3), etc., 3 is a first layer resin film, 4 is a first layer bonding pad made of, for example, aluminum (Al), and 5 is a first layer wiring. , 6 is the second layer resin film, 7 is the second layer resin film, and 7 is the second layer resin film.
8 indicates a layer bonding pad, 8 indicates a second layer wiring, and 9 indicates a third layer bonding pad.
図から明らかなように、本発明では、配線層が如何に多
層になつても、ボンディング・パッドは最下層から形成
するようにして、ボンディング時に大きな圧力が印加さ
れる部分の直下には樹脂皮膜を存在させていないので、
ボンディング時に半導体装置が損壊することはない。As is clear from the figure, in the present invention, no matter how many wiring layers there are, bonding pads are formed from the bottom layer, and a resin film is placed directly under the part where large pressure is applied during bonding. Since it does not exist,
The semiconductor device will not be damaged during bonding.
尚、ボンディング・パッドの材料がアルミニウムである
場合、樹脂皮膜に被着させるよりも二酸化シリコン膜、
燐硅酸ガラス膜、酸化アルミニウム膜等に被着させた方
がはるかに密着性が良好である。以上の説明で判るよう
に、本発明に依れば、例えば燐硅酸ガラス膜の如き絶縁
膜よりも耐湿性等の点で優れた特性を有する樹脂皮膜を
用いながら、ボンディング・パッドは極めて強固に形成
することができるので、ボンデイング時にパツドに大き
な圧力が加えられても、半導体装置が変形してパツドの
金属皮膜が剥離する等の損傷を受けることはない。If the material of the bonding pad is aluminum, a silicon dioxide film, rather than a resin film, is used.
Adhesion is much better when it is adhered to a phosphosilicate glass film, an aluminum oxide film, or the like. As can be seen from the above explanation, according to the present invention, bonding pads can be made extremely strong while using a resin film that has superior moisture resistance properties than insulating films such as phosphosilicate glass films. Therefore, even if a large pressure is applied to the pad during bonding, the semiconductor device will not be deformed and the metal film of the pad will not be damaged, such as peeling off.
また、各配線層に対応するボンデイング・パツドは、同
一位置に積層されているので、配線と接続して形成した
場合の段差を少なくすることができ、断線を生ずる虞が
なくなる。Further, since the bonding pads corresponding to each wiring layer are stacked at the same position, the difference in level when formed in connection with the wiring can be reduced, and there is no possibility of disconnection.
図は本発明一実施例を表す半導体装置の要部切断側面図
である。
図に於いて、１は基板、２は絶縁膜、３は樹脂皮膜、４
はボンデイング・パツド、５は配線層、６は樹脂皮膜、
７はボンデイング・パツド、８は配線層、９はボンデイ
ング・パツドをそれぞれ示す。The figure is a cutaway side view of essential parts of a semiconductor device representing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an insulating film, 3 is a resin film, and 4 is a
is a bonding pad, 5 is a wiring layer, 6 is a resin film,
7 represents a bonding pad, 8 represents a wiring layer, and 9 represents a bonding pad.
Claims (1)
の配線層にそれぞれ対応すると共に前記樹脂皮膜を介す
ることなく同一位置に積層して形成されたボンディング
・パッドとを備えてなることを特徴とする半導体装置。1 A plurality of wiring layers insulated between layers with a resin film, and bonding pads corresponding to the plurality of wiring layers and laminated at the same position without intervening the resin film. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52016714A JPS5923111B2 (en) | 1977-02-17 | 1977-02-17 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52016714A JPS5923111B2 (en) | 1977-02-17 | 1977-02-17 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53101980A JPS53101980A (en) | 1978-09-05 |
| JPS5923111B2 true JPS5923111B2 (en) | 1984-05-30 |
Family
ID=11923926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52016714A Expired JPS5923111B2 (en) | 1977-02-17 | 1977-02-17 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923111B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63129920U (en) * | 1987-02-19 | 1988-08-25 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666366B2 (en) * | 1981-06-24 | 1994-08-24 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPH0622256B2 (en) * | 1988-06-24 | 1994-03-23 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPS6427241A (en) * | 1988-06-24 | 1989-01-30 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1977
- 1977-02-17 JP JP52016714A patent/JPS5923111B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63129920U (en) * | 1987-02-19 | 1988-08-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53101980A (en) | 1978-09-05 |
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