JPH0666366B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is particularly applicable to a large-scale integrated circuit device (to be referred to as an LS hereinafter) whose layout is designed by a design technique such as CAD (Computer Aid cd Design) or DA (Design Automation).
It may be referred to as I)).

This kind of layout design is performed by using a computer especially from the viewpoints of designing various types of LSIs, shortening the design period, reducing the design man-hours, and improving the design quality. Determine virtual coordinates in advance,
A design automation method for forming an interconnection layer, a through hole, a contact hole, each circuit element, etc. at a predetermined coordinate position has been introduced. In this specification, the pitch of the virtual coordinates is particularly referred to as a "system wiring pitch", and the pitch of the wiring running in a large number of unit cells provided on the semiconductor wafer is referred to as a "cell wiring pitch".

The present inventors have proposed a CMOS LSI as a method of DA design.
In the unit cell circuit element formation region of the semiconductor wafer (semiconductor pellet), along a virtual coordinate, a multi-layered or single-layered conductor extending in the vertical and horizontal directions or in one direction, and further, between the unit cells, a virtual coordinate is formed. Along with this, a method of providing a multi-layered conductor extending in the vertical and horizontal directions and performing interconnection between the unit cells for providing one logic circuit function and between the unit cells by selecting through holes and contact holes was examined.

However, in a MOS LSI such as a CMOS logic circuit, when the wiring on the circuit element is formed of a single layer of aluminum wiring, it is not particularly difficult to understand this aluminum wiring and observe the internal signal. However, as the degree of integration increases, a multilayer wiring structure of aluminum is required.However, since a measurement probe cannot be directly applied to the aluminum wiring in the lower layer, the internal wiring structure cannot be used for product debugging and failure analysis. It was found that the signal waveform could not be observed accurately. Therefore, it is difficult to accurately identify the cause of product defects during the manufacturing process, feed it back to the initial stage of the process, and set normal manufacturing conditions early.
(Turn Around Time) becomes long. On the other hand, even if it is attempted to inspect the internal electrical state by using an indirect potential observing means using a low acceleration SEM, the amplitude of the detection signal is not constant because the film thickness of the interlayer insulating film is not uniform, and the inspection is performed. It has also been found that the operation at time is not easy.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device which can easily and accurately observe signals inside an IC having multi-layered wiring and can significantly reduce TAT. To this end, according to the present invention, a semiconductor integrated circuit device having a multilayer wiring structure is formed by an automatic design method in which virtual coordinates are determined on a semiconductor substrate and wiring layers, through holes, circuit elements, etc. are provided at predetermined virtual coordinate positions. In the method for manufacturing a semiconductor integrated circuit device, the step of providing the position of an observation terminal for measuring the characteristics of a predetermined circuit element so as to be located at the intersection of the virtual coordinates during the automatic design, provided by the automatic design method. When forming each wiring layer of multi-layer wiring,
A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a multi-layered observation terminal by laminating a conductor layer of the same material as the conductor layer forming each wiring layer at the observation terminal formation location. To do.

An embodiment in which the present invention is applied to a VLSI including a CMOS logic circuit will be described below in detail with reference to the drawings.

In FIG. 1, each logic block 1 having a medium-scale logic function is provided in a semiconductor chip 2. Between each logic block, A2 (A wiring of the second layer) and A1 (A wiring of the first layer) of the multilayer wiring are provided. ), Etc., are connected to each other to form a system having one large-scale logical function as a whole. As shown in FIG. 2, the logic block 1 itself is made up of columns of unit cells 5 provided in large numbers between the power supply terminals 3 and 4 at both ends, and polysilicon lines PS and A1 are provided between the columns or rows of the unit cells. Wirings connected with each other and jumping over, for example, one column are made at A2. The unit cell 5 is, for example, NOR, OR, AN.
Like logic circuits such as D, NAND, flip-flop,
It consists of cells with small unit logic functions.

In creating such a VLSI, from the viewpoint of shortening the design period, reducing the design man-hours, and improving the design quality, the CAD performs the layout and wiring design or the layout design using an electronic computer. Introducing a design automation method of predetermining virtual coordinates on a semiconductor wafer and forming an interconnection layer, a through hole, a contact hole, each circuit element, etc. at a predetermined coordinate position.

In this layout design, as shown in FIG. 3, regular grid-like coordinates are virtually provided in advance in the XY directions on a semiconductor wafer or chip, and interconnections are located at predetermined coordinate positions, and the grid points are located at the grid points. Programming is done so that there are through holes or contact holes for interconnection. That is, the above A1 is in the lateral direction and A2 is P.
In the vertical direction between S, they are arranged so as to be present on virtual coordinates at equal intervals, and as a whole, a regular XY
Forming the coordinates. In FIG. 3, the area of each unit cell 5 is shown by hatching, but adjacent cells may be connected by A12-A2-A1-PS as a multilayer wiring. Although a third-layer A broken line A3 can be further provided on A2, the A wiring and PS wiring of each layer including A3 are overlapped with each other in order to reduce a step and prevent disconnection of the wiring. It is located between other wires so that it does not exist.

As shown in FIG. 3, each wiring is provided along a pitch of predetermined coordinate, that is, along the system wiring pitch. What is important in this example is that the system wiring pitch is as close as possible. While occupying a smaller area on the layout by reducing the size, the observation pad P ₁ or P ₂ for observing the internal signal in the above-mentioned multilayer wiring structure is provided on one of the unit cell examples, for example, on the output lead line of the inverter. (Or, for example, NAND of the other unit cell row
It is provided on the input lead-in line of).

In the observation pad P ₁ , as shown in FIGS. 4 and 5, the lowermost polysilicon wiring PS having a thickness of 0.35 μm, which is the output lead-out line of the element of one unit cell, is the field of the N-type silicon substrate S. Is guided over the SiO ₂ film I,
Thickness is 0 at the predetermined intersection (lattice point) of the above coordinates.
It is connected to the upper aluminum wiring A1 having a thickness of 0.8 μm through a through hole TH ₁ formed in the phosphosilicate glass film PSG1 having a thickness of 8 μm. Then, even on the same lattice point, the aluminum film A2 which are formed simultaneously with the second layer of A wiring provided in the through hole TH ₂ formed in a thickness 0.8μm phosphorus silicate glass film PSG2, the A2 Is a phosphosilicate glass film PSG3
Is connected to the aluminum film A3 provided in the through hole TH ₃ formed during the third layer A wiring. Thus, observations lowermost polysilicon wiring PS is, be connected to the uppermost A3 via the respective through holes TH ₁ to TH ₃ provided on the same grid point position, and wherein the drawer of the output of the internal element to the outside It constitutes the pad P ₁ .

According to the observation pad P ₂ which can be provided separately from the pad P ₁ , as shown in FIGS. 6 and 7, A 1 is provided below the A 2 to provide an input to the element of the other unit cell. It is, and the upper surface of A2 is connected to the aluminum film A3 in the same manner as described above via a through hole TH ₃ glass film PSG3.

In each of the observation pads P ₁ and P ₂ described above, PS or A2 as an output lead line is drawn as a vertical pad structure in which the PS or A2 is pulled out to the uppermost A3 on the same coordinate grid point on the system wiring pitch. Therefore, by applying a potential observing probe to A3, the internal signal waveform or the internal signal can be directly measured, and the observation becomes extremely easy and accurate. Therefore, it is possible to determine whether the unit cell is good or bad based on this measured value, and immediately set the cause of the defect to the manufacturing process by feeding back to the normal condition, which not only improves the yield of the product but also the effective TAT. Shortening can be realized. Also, each pad P ₁ ,
The formation position of P ₂ , especially through holes TH1 to TH3 is C
Since it exists on a grid point that is convenient for the layout design by AD, the position setting can be performed with very good workability. Note that the above example is for the case of the three-layer wiring of aluminum, but in the case of the two-layer wiring, the through hole TH3 and the aluminum film A3 are omitted, so the measurement probe makes direct or indirect contact with A2. I will let you.

Next, a concrete example of the unit cell having the above-mentioned observation pad at the output point will be described with reference to FIGS.

In the CMOS logic circuit that constitutes the unit cell 5, in particular, as clearly shown in FIG.
P channel MOSFET 7 and N channel MOS
An FET section 8 is provided, and polysilicon gate electrodes PS ₁ , PS ₂ , P common to both FET sections are provided.
S ₃ , PS ₄ , and PS ₅ extend in parallel to the cell peripheral portion, and terminals A, B, C, D, E, A ′, and
B ', C', D'and E'are formed respectively. What is important here is that these terminals are arranged with the same pitch as the polysilicon wiring PS shown in FIG. This pitch is 1, in the lateral direction of FIG.
3, 5, 7, 9 correspond to system wiring pitches indicated by odd numbers. In order to cope with this, in this example, the following unique ideas are made to the shapes of the gate electrodes PS _{1 to} PS ₅ . A wirings 11, 12, 13 are formed at appropriate positions with respect to the respective FET ⁺ side P ⁺ type regions 9 and the FET 8 side N ⁺ type regions 10 formed by the ion implantation method or the diffusion method using each gate electrode as a mask. , 14 and 15 contact with ohmic contacts 16, 17, 1
8, 19, 20, 21, 22, 23, 24 and 25 are formed respectively. It should be noted here that the contact holes 16 to 20, 21 to 25 are not juxtaposed laterally side by side and the gate electrode runs between the contact holes, but the contact holes are arranged as shown in FIG. They are arranged vertically with a certain regularity, and are bent at an angle of about 45 ° near a predetermined contact hole as needed.

In this way, by bending the gate electrode at a necessary position, each contact hole, for example, the holes 17 and 2,
As compared with the case where 0 and 18 are arranged side by side in the horizontal direction, the gate electrodes PS ₄ and PS ₅ are kept at a predetermined distance from each hole even if they are alternately arranged vertically as shown in FIG. Can be provided. That is, for example, when the contact holes 17 and 20 are arranged side by side, the distance D between the holes can be reduced to a smaller distance D ′ by arranging the contact holes 17 and 20 in the upper and lower diagonal directions according to this example. . For example, if D is about 10 μm, D ′ is about 8 μm.
It can be m. By appropriately forming such a positional relationship between the contact hole and the gate electrode at each place, the terminals existing at both ends of each gate electrode can be reduced while reducing the distance between the contact holes (and thus between the gate electrodes) as a whole. It is possible to position AE and A'-E 'on the coordinates corresponding to the intended system wiring pitch.

The gate terminals A and D, B'and E'are connected to the A wiring 11
15 to 15, they are connected to each other by the A wirings 26 and 27 of the first layer. The A wiring of the first layer inside these cells can be preset to various patterns according to the desired unit logic function.
The wiring is arranged according to the system wiring pitch shown in FIG. 3 (in FIG. 8, the even-numbered coordinates displayed in the vertical direction). A
The wiring 11 is an N ⁺ formed adjacent to the P ⁺ type region 9.
A power supply line for supplying a power supply voltage V _DD to the substrate 6 via the mold region 28. Further, the A wiring 12 is applied to the wafer 29 by the voltage V via the P ⁺ type regions 30 formed at three positions in the P ⁻ type wafer 29 in the state of being adjacent to the N ⁺ type region 10.
It is a line for supplying _SS . In FIG. 9 showing a cross section taken along line XI-XI in FIG. 8 and FIG. 10 showing a cross section taken along line XX in FIG.
Reference numeral ₂ denotes a film, 32 denotes a gate oxide film, and 33 denotes a first layer phosphoric glass film. Although not shown in the drawing, the phosphosilicate glass film is an interlayer insulating film, and further on the A wiring of the first layer,
The second-layer A wiring may be coated, and the third-layer A wiring may be coated with a silane film as a passivation film.

By providing each wiring as shown in FIG. 8, a P channel MOSFE having each region 9 as a source or drain region is formed.
N channel M having TQ ₁ , Q ₂ , Q ₅ , Q ₇ , and Q ₈ and each region 10 as a source or drain region
_{OSFETQ 3, Q 4, Q 6} , Q 9, Q 10 is configured, these FET forms the connection has been one of the exclusive OR as Fig. 11 (Exclusive OR).
In this Exclusive OR, the contact holes in FIG. 8 must be alternately present at the places where a plurality of FETs are connected in parallel in a circuit. For this purpose, each region 9, 10 is It is desirable to have a length (channel width) sufficient to form a contact hole. Further, a contact hole is not always required at a place where a plurality of FETs are connected in series,
In consideration of the case where those FETs can be used in parallel, it is preferable to secure a channel width capable of forming contact holes in the upper and lower sides as described above. In addition, in FIG.
Five FETs are provided in each of the ET portions, but if it is desired to increase the number of elements, similar structures may be arranged side by side in the lateral direction of the figure.

In FIG. 8, in the CMOS, an observation pad P similar to the one described above is provided at the output point, and its position is taken on the grid point of the above-mentioned coordinates. As shown in detail in FIGS. 12 and 13, in this pad P, a polysilicon wiring 34 first runs on the field SiO ₃ film 31, and a through hole 35 of a phosphosilicate glass film 33 is formed on the polysilicon wiring 34. Then, the above A wiring 15 is deposited, and the phosphosilicate glass film 36 is further coated on this A wiring, and the through hole 37 formed in this is provided with the upper aluminum wiring material layer 38.
In the wiring material layer 38, a wide opening 41 is formed in the silicon nitride film 40 deposited by the plasma deposition method for passivation so that the measuring probe 39 can be applied sufficiently like an imaginary line.

If the probing is performed using the observation pad P configured as described above, the characteristics of the logic circuit in the unit cell can be measured easily and accurately. Therefore, a multi-layer wiring structure such as a CMOS type VLSI of this type can be obtained. Even if the device is complicated, the failure analysis can be fully performed.

Further, in this example, by bending the polysilicon gate electrode as an in-cell wiring in the vicinity of a necessary contact hole, the pitch can be reduced to match the minimum system wiring pitch. Both the system wiring pitch and the cell size can be reduced. As a result, the density of the unit cells can be increased, the number of wiring channels in the wiring channels between the unit cells can be significantly increased, and the pitch size itself can be significantly reduced.

Although the present invention has been illustrated above, the above-described embodiments can be further modified based on the technical idea of the present invention. For example, in the above-mentioned probing, the wiring material layer (pad) with which the probe is brought into contact may be the second layer of aluminum or the third layer of aluminum depending on the multilayer wiring structure. Further, the wiring, the interlayer insulating film, and the passivation film used may have various materials. Further, the bending angle and shape of the polysilicon gate electrode described above are not limited to those described above, but can be variously changed. Further, the gate electrode may be a metal gate other than polysilicon such as MoSi ₂ -polysilicon, or an A gate. The unit cell structure described above is exclusive N
Besides being applicable to OR, it can be modified for various logic circuits.

According to the present invention, as described above, the upper layer wiring is connected through the through hole formed on the predetermined portion of the lower layer wiring and is used as the observation pad. Observation can be performed easily and accurately. Therefore, the device manufacturing conditions can be corrected at an early stage due to a defect factor based on this observation result.

Further, since the observation pad is provided at a connection point (through hole) where the wiring layers provided in two layers other than the uppermost layer among the three or more wiring layers are intersections of the virtual coordinates. The position of the observation terminal can be easily set by the automatic design method, and there is no need to add a step for forming a through hole or a conductor layer for the observation terminal. There is no increase in the area of the device or the number of manufacturing steps. Moreover, according to the present invention, even when the pressure is slightly high when the probe is brought into contact with the observation terminal, the conductor in the lower wiring layer or the through hole serves as a buffer to prevent damage such as wiring breakage. effective.

[Brief description of drawings]

The drawings show an embodiment of the present invention. FIG. 1 is a schematic plan view of a semiconductor chip according to the first embodiment, FIG. 2 is a schematic plan view of one of its logic blocks, and FIG. FIG. 4 is a schematic view showing the coordinates showing the wiring pitch and the position of the observation pad on the interconnection, FIG. 4 is an enlarged plan view showing the observation pad position, and FIG. 5 is a sectional view taken along line VV of FIG. Figure,
FIG. 6 is an enlarged plan view showing another observation pad position, FIG. 7 is a sectional view taken along line VII-VII of FIG. 5 showing its structure, and FIG. 8 is a unit cell (CMOS logic circuit) constituting a logic block. FIG. 9 is an enlarged plan view, FIG. 9 is a longitudinal sectional view taken along line XI-XI of FIG. 8, and FIG. 10 is a longitudinal sectional view taken along line XX of FIG.
FIG. 11 is an Exclusive which constitutes the unit cell of FIG.
An equivalent circuit diagram of the OR, FIG. 12 is an enlarged plan view of the observation pad portion in FIG. 8, and FIG. 13 is XIII-XI in FIG.
It is sectional drawing which follows the II line. In the reference numerals used in the drawings, 1 is a logic block, 5 is a unit cell, and 7 is a P-channel MOSF.
ET portion, 8 N-channel MOSFET portion, 9 P ⁺ type region, 10 N ⁺ type region, 11 to 15 A wiring, 16
25 are contact holes, 28 are N ⁺ type power supply regions, 3
0 is a P ⁺ type power supply region, 34 is a polysilicon wiring, 38 is an A wiring material layer, 39 is a probe, 40 is a silicon nitride film, A1 is the first layer A wiring, and A2 is the second layer A.
Wirings, PS and PS _{1 to} PS ₅ are polysilicon gate electrodes, A to E and A ′ to E ′ are terminals, P, P ₁ and P ₂ are observation pads, and PSG _{1 to} PSG ₃ and 33 and 36 are phosphosilicates. The glass films TH1 to TH3 and 35 and 37 are through holes.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Sumiji Ueno, 1-280, Higashi Koikekubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Masao Kato, 1 Horiyamashita, Hadano, Kanagawa (56) References JP-A-56-19634 (JP, A) JP-A-53-23570 (JP, A) JP-A-53-101980 (JP, A) JP-A-53-25382 (JP , A) JP-A-57-192062 (JP, A) Actually developed Shou-53-66074 (JP, U)

Claims (1)

[Claims] 1. A virtual coordinate is determined in X and Y directions orthogonal to each other on a semiconductor substrate, and a wiring layer, a through hole, a circuit element, etc. are provided at predetermined virtual coordinate positions by an automatic design method, and the virtual design is obtained. In a method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure having three or more wiring layers based on the obtained data, in order to measure the characteristics of a predetermined circuit or element at the time of the automatic designing. And a step of providing the observation terminal at a position where wiring layers provided in two layers other than the uppermost layer among the three or more wiring layers are connected to each other and at a predetermined position which is an intersection of the virtual coordinates. When forming each wiring layer set by the above-mentioned automatic design method, the above-mentioned observation terminal is provided at a predetermined location set by the above-mentioned automatic design method, except for the above-mentioned uppermost layer which is connected to each other.
A step of forming a conductor layer that is deposited at the same time as a conductor layer that constitutes a wiring layer higher than one wiring layer, and a method of manufacturing a semiconductor integrated circuit device.