JPS5923114B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device for logic circuits that has a small chip area and speed-power product and can provide an arbitrary number of fan-outs.

Several semiconductor devices for logic circuits have been known in the past, one of which is the 12L (Integrated Injection) which has a high degree of integration and saves device area without requiring an isolation diffusion region or a diffusion resistor.
For example, a logical circuit element with a Logic) structure is
No. 35030.

An example of a NOR circuit configured with this structure is shown in FIG. 1, and its basic operating principle will be briefly explained. P-type diffusion regions P1, P2 and P3 are arranged in an n-type semiconductor substrate (Ni) and separated from each other. This P1 is the emitter,
A lateral transistor Tl is formed using Ni as a base and P2 as a collector, and a lateral transistor T3 is formed as having P1 as an emitter, N2 as a base and P3 as a collector. N2 and N3 regions in the semiconductor substrate N2 and P2 and P3 regions are formed by n-type diffusion. As a result, a vertical transistor T2 with Ni as an emitter, P2 as a base, and N3 as a collector
, N4 as the emitter, P3 as the base, and N3 as the collector, a vertical transistor T4 is obtained. Now, the operation of transistors Ti and T2 will be explained.

When a current I is applied to the emitter P, of the transistor Ti, the injected holes are partially collected in the collector P2 of the transistor Ti. As a result, P- of P, and N,
The n-junction is forward biased and electrons are injected into P2 from N1, which acts as the emitter of transistor T2. Therefore, when A is connected to a current source and input E1 is left floating, a collector current c flows through transistor T2. However, if a ground potential is applied to E1, Ic is prevented from flowing across the N2 collector region of transistor T2. PNP transistor T1 thus supplies current to the base of NPN transistor T2, which operates in the opposite direction. At this time, if E1 is in a floating state, the current applied to the PNP transistor T1 is
, and thus the transistor T2 becomes saturated conductive. However, when E1 is connected to ground conductivity, the current 1 applied to T1 flows through E, and cannot flow to the base of T2. In this case T2 is blocked. Considering the potential developed at the collector of T2, T1 and T2 form an inverting circuit. The relationship between the other transistors T3 and transistor T4 is also similar to the operation of the transistors T and T3 described above.

A NOR circuit is formed by these transistors T1 to T4. In the device with the conventional structure shown above, the N1 region is the emitter of the transistor T2 and the base of the transistor T1, so it is not allowed to have a high impurity concentration in order not to reduce the emitter injection efficiency of the transistor T1. It is about 1016at0m/Crit.

Therefore, the transistor T2 operates as a reverse transistor, and the efficiency of emitter injection from N2 to P2 is poor, and the common emitter current amplification factor HFE is usually very small, 2 to 3. Therefore, it is impossible to take a large number of fanouts from the collector N2. Furthermore, in order to prevent further reduction in HFE, the base P2 of the transistor T2 is kept at a relatively low impurity concentration, which increases the base resistance and slows down the calculation speed.
Further, since a reverse drift electric field is generated in the base region of the transistor T2, the carrier diffusion time is long, and the minority carrier accumulation time is also required, which slows down the calculation speed. In order to improve the above-mentioned drawbacks, the present invention has a structure equipped with a switching element of a new structure, has an arbitrary number of fan-outs, and has the ability to drive even a device with a large input drive current such as TTL. Another object of the present invention is to provide a logic circuit element having a small speed-power product and a small element area.

Hereinafter, one embodiment of the present invention will be described in detail based on FIG. 2. FIG. 2a is a schematic plan view of a partial main part of the device according to an embodiment of the present invention, and FIG. 2b is a partial schematic diagram when cut along the line BB' shown in FIG. 2a. Cross-sectional view, Figure 2c
2 is a schematic partial sectional view taken along the line CC' shown in FIG. 2a. In FIG. 2, reference numeral 1 denotes an n+ type substrate having a low resistivity, for example, about 0.001Ω·min, and is kept at the ground potential. 2 is a high resistivity film formed on the above 1, for example 5
It is an n-type layer of about 0 Ω.

3 and 4 are P+ type regions, and 3 and 4 are arranged close to each other, and the P+ type region 3 is a part of the region 2a, 2 of the n-type layer 2.
For example, it is formed in a mesh shape so as to partially surround b.

Regions 4, 2, and 3 constitute a lateral Pnp transistor T, l, and 4, 2, and 3 serve as an emitter, a base, and a collector, respectively. In this transistor Tll,
Since the base concentration is low and the emitter and collector concentrations are very high, the rate at which holes injected from the emitter reach the collector is much higher than in the conventional device structure shown in FIG.
Also, a part 2a of the region 2 surrounded by the p+ type region 3,
2b, when the potential of region 3 is 60nv, region 3 and region 2a,
2b is formed so as to be filled with a depletion layer by the diffusion of the Pn junction.

Furthermore, region 2a consists of multiple value regions surrounded by region 3, each of which has PN when the potential of region 3 is "0".
It is assumed that the junction is filled with a capacitive layer due to the diffusion potential. 5a and 5b are n+ type regions formed on the surface of the n layer 2, and 2, 3, 2a, 2b, 5a, and 5b constitute a switching element S1.

In this element S, 3 serves as a gate, 2a and 2b serve as conductive paths, and 1, 5a and 5b serve as electrode lead-out portions. In the device shown in FIG. 2, the terminal in region 4 is designated as bias terminal B, the terminal in region 3 is designated as input terminal 1, and the terminals in regions 5a and 5b are designated as output terminals 0, 02. Note that this output terminal 01
, 0, is not limited to two, but any number can be taken out.
The output terminal 0 commonly connects a plurality of conductive paths 2a. In this example, the conductive path 2a consists of three pieces. Next, the operation of this device will be explained.

A current of 1 B is constantly injected from terminal B.

If input terminal 1 is now in a floating state, transistor Tll
The holes injected from the emitter 4 of the transistor T
, l, that is, the gate 3 of the switching element S
The potential of increases to about +0.6V. Therefore, there is almost no depletion layer in the conductive path regions 2a and 2b of the switching element S1, and the depletion layer is reduced to 1-2a-5a or 1-2b-5b.
A conductive path is formed, and the output of terminals 01 and 02 is 60
It becomes ゛V. Next, when the terminal becomes the ground potential, that is, "0", the holes accumulated in the gate 3 of the switching element S are discharged through the terminal, and the gate 3 becomes 0V.

For this reason, the conductive path regions 2a and 2b of the switching element S are
As mentioned above, due to the diffusion voltage generated in the Pn junction between the gate 3 and the regions 2a and 2b, the regions 2a and 2b are filled with a depletion layer.
5a and 5b are electrically separated, and terminal 0 is in a floating state. Here, a plurality of conductive paths 2a are formed.
With this structure, the output terminal 01 can flow a large current. Simply increasing the area of the conductive path makes it impossible to fill the region 2a with a depletion layer when the potential of the gate 3 is at capi O', making it impossible to bring the output terminal 0 into a floating state. Also, in the structure of 02, rather than connecting multiple pieces to create an output terminal with a large current capacity,
The output terminal configuration allows for a much smaller area. In this way, the transistor Tl and the switching element S
and form an inverting circuit. FIG. 3 shows another embodiment of the invention.

1 means low resistivity, for example 0.001Ω? It is a ML-type substrate of about 100 mL, and is kept at ground potential.

2 is an n-type layer formed on the above 1 and having a high resistivity, for example, about 50Ω.

30 and 4 are p+ type regions formed from the surface of 2, and 30 and 4 are arranged close to each other. Formed in a mesh shape.

As shown in FIG. 2, the PNP transistor Tl, which is composed of circuits 4, 2, and 30, serves as the emitter, base, and collector, respectively. In this transistor Tl, the second
As shown in the figure, the base concentration is low and the emitter and collector concentrations are very high, so the rate at which the hole poured from the emitter reaches the collector is much higher than in the conventional structure. Also, when the potential of the region 30 is 0, parts 2a and 2b of the region 2 surrounded by the region 30 are filled with a depletion layer due to the diffusion potential of the Pn junction composed of the region 30, 2a, and 2b. is formed. 5a and 5b are ml-shaped regions formed on the surface of 2, and in the switching element S consisting of 1, 2, 5a, and 5b, 30 is a gate, and 2a, 2b, 5a, and 5b are
acts as a conductive path.

In particular, in the n+ type region 5a, the surface of the p type region 30 is inverted to the n+ type, and the respective conductive paths 2a are connected to each other. The terminal 4 becomes the bias terminal B, the terminal 30 becomes the input terminal 1, and the terminals 5a and 5b become the output terminals 01 and 02, and the operation is the same as that in FIG. 2.

The output terminal 0 is constituted by a plurality of conductive paths, and the output current capacity is increased as in FIG. 2. The device of the present invention does not use an inverted transistor structure unlike the conventional device, and transmits signals to terminals 01 and 02 only by opening and closing the gates. It has the advantage that only one can be selected and operated freely.

In addition, the bases of the transistors T, I and the switching element S, and the region 2 serving as the conductive path, can be selected to have as low a concentration as possible, for example, about 1014at0m-Cf3, and the injection efficiency of the transistor Tll can be greatly improved. At this time, the maximum dimension d of the so-called channel regions 2a and 2b is determined by the condition that the channel region is completely filled with a depletion layer at a diffusion potential of, for example, 0.6.

Furthermore, since the impurity concentration of the gate 3 of the switching element S can be arbitrarily selected to be high, which was not possible with the structure shown in FIG. 1, the gate resistance can be lowered and the calculation speed can be increased. are doing.

Furthermore, since the switching element S in FIGS. 2 and 3 operates with a large number of carriers, there is no accumulation effect of carriers as in the conventional structure, and the switching element S can operate easily and quickly even during a channel. Furthermore, in the conventional structure, a large collector current of the transistor T1 was required due to the small HFE of the transistor T2, but in this structure, the collector current is sufficient to charge the stray capacitance between the gate 3 of the switching element S and the conductive paths 2a and 2b. Therefore, the power of the transistor Tll can be made very small, and the operation of the switching element S is essentially different from the operation of the conventional transistor T2, and it is efficient and can handle a large switching current with a small area, so the area of the switching element can be made small. It also has advantages. Furthermore, in this structure, since a plurality of conductive paths are formed as shown in FIG. 2 2a, the current capacity that can be passed is large, that is, the effect as an output stage is large. (DiOdTransi
stOrLOgic), TTL (Tran-SistO
rTransistOrLOgic) etc. can be directly driven.

FIG. 4 shows a connection between the semiconductor device of the present invention and TTL.

Tll is a PNP transistor of the present invention, S is a switching element of the present invention, and 0, 02 are output terminals thereof.
On the other hand, in TTL, 7, 8, 9, and 11 are transistors, 10 is a diode, 12 is a resistor for base current of transistor 7, and resistors 13 and 14 are resistors for current limiting of transistors 8 and 9. 15 is a power supply terminal, and 16 is a TTL output terminal.

In TTL, the base current of the transistor 7 is relatively large, and to drive it, it is necessary to sink a current of about 1 to 2 rr1A.

However, since there is only one conductive path 2b to absorb this current at the output terminal 02 in FIG. 2, it cannot be driven. By making this an output terminal such as 0 in FIG. 2 and optimizing the number of conductive paths 2a, TTL can be directly driven.
That is, according to the present invention, direct TTL can be easily driven. In this manner, the semiconductor device of the present invention is also effective for interface circuits.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a conventional IIL-structured logic circuit element, and FIG. 2 shows a logic circuit element according to an embodiment of the present invention.
a is a schematic plan view of the main part, B and c are respectively AOB-B',
3 is a structural diagram of another embodiment of the logic circuit element of the present invention, and FIG. 4 is a cross-sectional view of the logic circuit element of the present invention and T
It is a connection diagram of a TL circuit. 1...n+ substrate, 2...n uniform layer (base), 2a, 2b...conducting path region, 3, 30
・・・・・・P+ type region (collector), 4・・・・・・
p+ type region (emitter), 5a, 5b...n+
Shape region, Tl,... Lateral transistor, S.
...Switching element.

Claims (1)

Claims: 1. In a semiconductor body having one conductivity type serving as a base region of a lateral transistor, conductivity types of the other conductivity type serving as an emitter region and a collector region of the lateral transistor are spaced apart from each other. a plurality of vertical conductive paths of one conductivity type formed in the collector region of the lateral transistor, and the collector region of the lateral transistor is a gate region; 1. A semiconductor device comprising a switching element, wherein a conductive path of the switching element is filled with a depletion layer due to a diffusion potential of the gate region, and has an output terminal that commonly connects the plurality of conductive paths. 2. A current source connected to the emitter region of the lateral transistor, an input signal source connected to the collector region of the transistor, and a plurality of conductive paths of the switching element in the conductive path, and a semiconductor substrate that does not become the base region of the transistor. 2. The semiconductor device according to claim 1, further comprising an output terminal connected at one end of the semiconductor device. 3. The semiconductor device according to claim 1 or 2, further comprising one conductive type low resistivity region connected to a plurality of conductive paths on the surface of the semiconductor substrate.