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JPS592377B2 - Method for manufacturing semiconductor devices - Google Patents
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JPS592377B2 - Method for manufacturing semiconductor devices - Google Patents

Method for manufacturing semiconductor devices

Info

Publication number
JPS592377B2
JPS592377B2 JP9291278A JP9291278A JPS592377B2 JP S592377 B2 JPS592377 B2 JP S592377B2 JP 9291278 A JP9291278 A JP 9291278A JP 9291278 A JP9291278 A JP 9291278A JP S592377 B2 JPS592377 B2 JP S592377B2
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
oxide film
silicon oxide
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9291278A
Other languages
Japanese (ja)
Other versions
JPS5519874A (en
Inventor
東彦 阿部
邦明 三宅
章 西本
夏朗 坪内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9291278A priority Critical patent/JPS592377B2/en
Publication of JPS5519874A publication Critical patent/JPS5519874A/en
Publication of JPS592377B2 publication Critical patent/JPS592377B2/en
Expired legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は半導体素子の製造方法、特に単結晶シリコン基
板上の酸化シリコン膜の膜厚の少なくとも2倍以上の酸
化シリコン膜をシリコン基板と多結晶シリコン膜との同
時酸化により多結晶シリコン膜表面に生成させる半導体
素子の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular, a silicon oxide film having a thickness at least twice the thickness of a silicon oxide film on a single crystal silicon substrate is simultaneously oxidized with a silicon substrate and a polycrystalline silicon film. The present invention relates to a method for manufacturing a semiconductor element formed on the surface of a polycrystalline silicon film.

一般に多結晶シリコン膜を有するシリコンゲートモス集
積回路の製造方式は、自己整合型の製造方式であり、高
集積密度モス集積回路の製造方法として広く実用化され
ている。
Generally, the manufacturing method of silicon gate MOS integrated circuits having a polycrystalline silicon film is a self-aligned manufacturing method, and is widely put into practical use as a manufacturing method of high integration density MOS integrated circuits.

さらに、一定面積内の半導体素子数を向上させ、集積密
度を一層向上させる方法としては、多結晶シリコン膜を
二層構造とする二層多結晶シリコン膜製造のモス集積回
路が知られている。このような構造の半導体素子は、ダ
イナミックメモリ用のメモリ素子として用いられている
。第1図はこのようなメモリ素子の断面構造を示したも
のである。同図において、このメモリ素子は、シリコン
基板1と、熱酸化による酸化シリコン膜2と、第一層目
の多結晶シリコン膜3と、シリコン基板1上の第2トラ
ンジスタ用酸化シリコン膜4と、第一層多結晶シリコン
膜3と第二層多結晶シリコン膜5とを絶縁分離するため
の酸化シリコン膜4とから構成されている。このように
構成された半導体素子において、第一層の多結晶シリコ
ン膜3と第二層多結晶シリコン膜5とを絶縁分離するた
めの酸化シ、リコン膜4は、通常第一層多結晶シリコン
膜3の熱酸化によつて生成され、このとき同時にシリコ
ン基板1上にも所定の膜厚の酸化シリコン膜4が生成さ
れる。そして、この酸化シリコン膜4の膜はトランジス
タの動作を規定するしきい値電圧と直接的に関連するた
め、一定の膜厚内に抑えることが必要である。一方、酸
化シリコン膜4の特性上、つまり第一層多結晶シリコン
膜3と第二層多結晶シリコン膜5との絶縁分離膜として
用いるため、出来るだけ膜厚が厚い方が好ましく、また
、回路全体の特性向上の点からも好ましい。ところが、
この酸化シリコン膜4は、第一層多結晶シリコン膜3の
酸化工程によつてシリコン基板1上にも同時に生成され
るため、従来の酸化方法では、シリコン基板1上の酸化
シリコン膜4と多結晶シリコン膜3上に成長する酸化シ
リコン膜4との膜厚比がほぼ1.5〜1.7程度であり
、この膜厚比を2倍以上に形成することは極めて困難で
あつた。特に多結晶シリコン膜3に高濃度に不純物が拡
散されている場合は、この膜3を高温度で長時間酸化処
理すると、多結晶シリコン膜3の膜表面が著しく荒れ、
層間の耐電圧特性の低下による不良発生および信頼性の
低下などの原因となつていた。したがつて、本発明の目
的は、上記の欠点を除去するためになされたものであり
、予め多結晶シリコン膜の表面近傍に膜中より高濃度の
不純物を注入しておき、高圧酸化性雰囲気中で単結晶シ
リコン基板と同時に比較的低温度で熱酸化することによ
つて単結晶シリコン基板表面に成長する酸化シリコン膜
の膜厚より厚い酸化シリコン膜を多結晶シリコン膜表面
に生成させるようにした半導体素子の製造方法を提供す
ることにある。
Further, as a method for increasing the number of semiconductor elements within a certain area and further improving the integration density, a MOS integrated circuit manufactured using a two-layer polycrystalline silicon film in which a polycrystalline silicon film has a two-layer structure is known. A semiconductor element having such a structure is used as a memory element for dynamic memory. FIG. 1 shows a cross-sectional structure of such a memory element. In the figure, this memory element includes a silicon substrate 1, a silicon oxide film 2 formed by thermal oxidation, a first layer polycrystalline silicon film 3, and a second transistor silicon oxide film 4 on the silicon substrate 1. It is composed of a silicon oxide film 4 for insulating and separating a first layer polycrystalline silicon film 3 and a second layer polycrystalline silicon film 5. In a semiconductor device configured in this way, the silicon oxide film 4 for insulating and separating the first layer polycrystalline silicon film 3 and the second layer polycrystalline silicon film 5 is usually made of first layer polycrystalline silicon film 4. It is produced by thermal oxidation of the film 3, and at the same time, a silicon oxide film 4 of a predetermined thickness is also produced on the silicon substrate 1. Since the thickness of the silicon oxide film 4 is directly related to the threshold voltage that defines the operation of the transistor, it is necessary to keep the thickness within a certain range. On the other hand, due to the characteristics of the silicon oxide film 4, that is, since it is used as an insulating separation film between the first layer polycrystalline silicon film 3 and the second layer polycrystalline silicon film 5, it is preferable that the film is as thick as possible. It is also preferable from the viewpoint of improving overall characteristics. However,
This silicon oxide film 4 is simultaneously generated on the silicon substrate 1 by the oxidation process of the first layer polycrystalline silicon film 3, so in the conventional oxidation method, the silicon oxide film 4 on the silicon substrate 1 and the polycrystalline silicon film 4 are The film thickness ratio of the silicon oxide film 4 grown on the crystalline silicon film 3 is about 1.5 to 1.7, and it is extremely difficult to form a film with this film thickness ratio of twice or more. In particular, when impurities are diffused at a high concentration into the polycrystalline silicon film 3, if this film 3 is oxidized at high temperature for a long period of time, the surface of the polycrystalline silicon film 3 will become extremely rough.
This has been a cause of defects and a decrease in reliability due to a decrease in the withstand voltage characteristics between the layers. Therefore, an object of the present invention has been made to eliminate the above-mentioned drawbacks, and involves implanting impurities in a higher concentration in advance near the surface of a polycrystalline silicon film than in the film, and then placing the film in a high-pressure oxidizing atmosphere. By thermally oxidizing the single-crystal silicon substrate at a relatively low temperature at the same time as the single-crystal silicon substrate, a silicon oxide film that is thicker than the silicon oxide film that grows on the surface of the single-crystal silicon substrate is generated on the surface of the polycrystalline silicon film. An object of the present invention is to provide a method for manufacturing a semiconductor device.

以下図面を用いて本発明による半導体素子の製造方法に
ついて詳細に説明する。第2図a−dは本発明による半
導体素子の製造方法の一実施例を説明するための要部断
面工程図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the drawings. 2A to 2D are cross-sectional process diagrams of essential parts for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention.

これらの図において、まず同図aに示すようにシリコン
基板1の酸化シリコン膜2上面には、所定の膜厚を有す
る多結晶シリコン膜3が形成され、この多結晶シリコン
膜3内には、所定の濃度を有する不純物が含まれている
。このような構造において、この多結晶シリコン膜3の
表面近傍に例えばこの膜3内に含まれている不純物と同
種類の不純物を高濃度に注入し、高濃度不純物拡散層6
を形成する。この場合、この拡散層6の形成には、例え
ばイオン注入法が用いられる。次に同図bに示すように
公知の写真製版技術により多結晶シリコン膜3、拡散層
6のノぐターニングを行なう。この工程は、例えば四弗
化炭素を用いたガスプラズマを用いたプラズマエツチン
グ法が用いられる。次いで同図cに示すように弗酸溶液
を用いた湿式エツチング法あるいはガスプラズマを用い
た選択エツチング法によりシリコン基板1上の酸化シリ
コン膜2の一部を除去し、シリコン基板1の一部分を露
出させる。このような構造のものを例えば酸化温度80
0℃,H2/02雰囲気圧4.5kg/CTilの高圧
酸化性雰囲気中に所定の時間浸漬して同図dに示すよう
にシリコン基板1の表面1aに例えば膜厚1000への
酸化シリコン膜7を成長させると、例えば高濃度不純物
拡散層6の比抵抗が20Ω/口程度の場合には、多結晶
シリコン膜3上に約3500人と約3.5倍の膜厚を有
する酸化シリコン膜7が形成される。さらに高濃度不純
物拡散層6の比抵抗に換算して10Ω/口程度の場合に
は、同一高圧酸化条件下では約5倍程度の膜厚の酸化シ
リコン膜7が多結晶シリコン膜3上に形成される。また
、同一酸化圧力、例えば4.5Kg/d下でこの酸下膜
厚比を大きくするためには、酸化温度を例えば800℃
から700℃に下げれば良く、また酸化温度を700℃
に固定した場合には酸化圧力を大きくすれば良い。この
ように高圧酸化において、酸化温度、多結晶シリコン膜
3表面の高濃度不純物層の不純物濃度を適当に組み合わ
せることにより、容易にシリコン基板1上に酸化シリコ
ン膜7の膜厚の2倍以上の酸化シリコン膜7を多結晶シ
リコン膜3上に形成することができる。第3図a−dは
本発明による半導体素子の製造方法の他の実施例を説明
するための要部断面工程図である。
In these figures, first, as shown in figure a, a polycrystalline silicon film 3 having a predetermined thickness is formed on the upper surface of a silicon oxide film 2 of a silicon substrate 1. Contains impurities with a predetermined concentration. In such a structure, impurities of the same type as those contained in the polycrystalline silicon film 3 are implanted in a high concentration near the surface of the polycrystalline silicon film 3 to form a high concentration impurity diffusion layer 6.
form. In this case, for example, ion implantation is used to form the diffusion layer 6. Next, as shown in FIG. 4B, the polycrystalline silicon film 3 and the diffusion layer 6 are turned by a known photolithography technique. In this step, for example, a plasma etching method using gas plasma using carbon tetrafluoride is used. Next, as shown in FIG. 3c, a part of the silicon oxide film 2 on the silicon substrate 1 is removed by wet etching using a hydrofluoric acid solution or selective etching using gas plasma, and a part of the silicon substrate 1 is exposed. let For example, the oxidation temperature of such a structure is 80
A silicon oxide film 7 is formed on the surface 1a of the silicon substrate 1 to a thickness of, for example, 1000 by immersing it in a high-pressure oxidizing atmosphere of 0° C. and H2/02 atmospheric pressure of 4.5 kg/CTil for a predetermined time, as shown in FIG. For example, if the resistivity of the high concentration impurity diffusion layer 6 is about 20Ω/hole, about 3,500 silicon oxide films 7 with about 3.5 times the film thickness will grow on the polycrystalline silicon film 3. is formed. Furthermore, if the specific resistance of the high concentration impurity diffusion layer 6 is about 10 Ω/hole, a silicon oxide film 7 about five times thicker will be formed on the polycrystalline silicon film 3 under the same high-pressure oxidation conditions. be done. In addition, in order to increase the film thickness ratio under acid under the same oxidation pressure, for example 4.5 kg/d, the oxidation temperature must be set to 800°C, for example.
It is sufficient to lower the oxidation temperature from 700℃ to 700℃.
If it is fixed at , the oxidation pressure can be increased. In this way, in high-pressure oxidation, by appropriately combining the oxidation temperature and the impurity concentration of the high-concentration impurity layer on the surface of the polycrystalline silicon film 3, it is easy to form a film on the silicon substrate 1 with a thickness that is more than twice the thickness of the silicon oxide film 7. A silicon oxide film 7 can be formed on the polycrystalline silicon film 3. FIGS. 3a to 3d are cross-sectional process diagrams of essential parts for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention.

これらの図において、まず、同図aに示すようにシリコ
ン基板1の酸化シリコン膜2上面には、所定の膜厚を有
する多結晶シリコン膜3が形成され、この多結晶シリコ
ン膜3内には所定の濃度を有する不純物が含まれている
。次に同図bに示すように公知の写真製版技術により多
結晶シリコン膜3のパターニングを行なう。次いで同図
cに示すようにイオン注入法などの不純物注入法によつ
て上記パターニングされた多結晶シリコン膜3の表面に
高濃度不純物拡散層6を形成する。このとき、同図cに
示されているように酸化シリコン膜2の表面層にも不純
物が拡散されて膜表面に高濃度不純物拡散層6が形成さ
れる。この場合、多結晶シリコン膜3の上記エツチング
の側面3aにも酸化シリコン膜2の表面2aと同時に同
様の高濃度不純物拡散層6が形成される。次いで酸化シ
リコン膜2上の拡散層6は、同図dに示すように上記選
択エツチング法により除去し、シリコン基板1の一部分
を露出させる。このような構造のものを上記実施例で説
明した酸化温度、酸化圧力による高圧酸化および多結晶
シリコン膜3表面の高濃度不純物層の不純物濃度を適当
に組み合わせることによつて、図示しないが、第2図d
に示したものとほぼ同様にシリコン基板1上に酸化シリ
コン膜7の膜厚の2倍以上の酸化シリコン膜7を多結晶
シリコン膜3上に形成することができる。以上説明した
ように本発明による半導体素子の製造方法によれば、シ
リコン基板上に形成される酸化シリコン膜の膜厚の2倍
以上の酸化シリコン膜を多結晶シリコン膜上に容易に形
成できるため、半導体素子、集積回路の諸特性および信
頼性を大幅に向上させることができる極めて優れた効果
が得られる。
In these figures, first, as shown in figure a, a polycrystalline silicon film 3 having a predetermined thickness is formed on the upper surface of a silicon oxide film 2 of a silicon substrate 1. Contains impurities with a predetermined concentration. Next, as shown in FIG. 3B, the polycrystalline silicon film 3 is patterned using a known photolithography technique. Next, as shown in FIG. 3C, a high concentration impurity diffusion layer 6 is formed on the surface of the patterned polycrystalline silicon film 3 by an impurity implantation method such as an ion implantation method. At this time, impurities are also diffused into the surface layer of the silicon oxide film 2, forming a high concentration impurity diffusion layer 6 on the film surface, as shown in FIG. In this case, a similar high concentration impurity diffusion layer 6 is formed on the etched side surface 3a of the polycrystalline silicon film 3 at the same time as the surface 2a of the silicon oxide film 2. Next, the diffusion layer 6 on the silicon oxide film 2 is removed by the selective etching method described above, as shown in FIG. 4D, to expose a portion of the silicon substrate 1. Although not shown in the figure, such a structure can be obtained by appropriately combining the oxidation temperature, high-pressure oxidation using oxidation pressure, and impurity concentration of the high-concentration impurity layer on the surface of the polycrystalline silicon film 3 as explained in the above embodiment. Figure 2 d
A silicon oxide film 7 having a thickness more than twice the thickness of the silicon oxide film 7 can be formed on the polycrystalline silicon film 3 on the silicon substrate 1 in substantially the same manner as shown in FIG. As explained above, according to the method for manufacturing a semiconductor device according to the present invention, a silicon oxide film having a thickness more than twice the thickness of a silicon oxide film formed on a silicon substrate can be easily formed on a polycrystalline silicon film. , extremely excellent effects can be obtained that can significantly improve various characteristics and reliability of semiconductor devices and integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体素子の一例を示す要部断面図、第
2図a−dは本発明による半導体素子の製造方法の一実
施例を説明するための要部断面工程図、第3図a−dは
本発明による半導体素子の製造方法の他の実施例を説明
するための要部断面工程図である。 1・・・・・・シリコン基板、1a・・−・・表面、2
・・・・・・酸化シリコン膜、2a・・・・・・表面、
3・・・・・・第一層多結晶シリコン膜、3a・・・・
・・側面、4・・・・・・酸化シリコン膜、5・・・・
・・第二層多結晶シリコン膜、6・・・・・・高濃度不
純物拡散層、7・・・・・・酸化シリコン膜。
FIG. 1 is a sectional view of a main part showing an example of a conventional semiconductor device, FIGS. Figures a to d are cross-sectional process diagrams of main parts for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention. 1...Silicon substrate, 1a...Surface, 2
...Silicon oxide film, 2a...Surface,
3...First layer polycrystalline silicon film, 3a...
...Side surface, 4...Silicon oxide film, 5...
. . . second layer polycrystalline silicon film, 6 . . . high concentration impurity diffusion layer, 7 . . . silicon oxide film.

Claims (1)

【特許請求の範囲】[Claims] 1 所定の不純物濃度を含有した多結晶シリコン膜表面
の一定距離内に不純物注入法により局所的に該膜中の不
純物濃度より高濃度の不純物拡散層を形成する工程と、
前記表面部に高濃度不純物拡散層を有する多結晶シリコ
ン膜と同一基板内に単結晶シリコン基板表面を露出させ
る工程と、前記単結晶シリコン基板表面と前記表面部に
高濃度不純物拡散層を形成した多結晶シリコン膜とを少
なくとも大気圧より高い高圧酸化性雰囲気中で酸化して
前記単結晶シリコン基板表面に成長する酸化シリコン膜
の膜厚より十分厚い酸化シリコン膜を前記多結晶シリコ
ン膜表面に生成する工程とからなることを特徴とする半
導体素子の製造方法。
1. locally forming an impurity diffusion layer with a higher concentration than the impurity concentration in the film by an impurity implantation method within a certain distance of the surface of a polycrystalline silicon film containing a predetermined impurity concentration;
exposing a single crystal silicon substrate surface in the same substrate as a polycrystalline silicon film having a high concentration impurity diffusion layer on the surface portion, and forming a high concentration impurity diffusion layer on the single crystal silicon substrate surface and the surface portion. oxidizing the polycrystalline silicon film in a high-pressure oxidizing atmosphere higher than at least atmospheric pressure to produce a silicon oxide film on the surface of the polycrystalline silicon film that is sufficiently thicker than the silicon oxide film grown on the surface of the single-crystal silicon substrate. A method for manufacturing a semiconductor device, comprising the steps of:
JP9291278A 1978-07-28 1978-07-28 Method for manufacturing semiconductor devices Expired JPS592377B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9291278A JPS592377B2 (en) 1978-07-28 1978-07-28 Method for manufacturing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9291278A JPS592377B2 (en) 1978-07-28 1978-07-28 Method for manufacturing semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5519874A JPS5519874A (en) 1980-02-12
JPS592377B2 true JPS592377B2 (en) 1984-01-18

Family

ID=14067684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9291278A Expired JPS592377B2 (en) 1978-07-28 1978-07-28 Method for manufacturing semiconductor devices

Country Status (1)

Country Link
JP (1) JPS592377B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61137346A (en) * 1984-12-10 1986-06-25 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS5519874A (en) 1980-02-12

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