JPH05867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an MIS type semiconductor device, and particularly to a device with a novel structure using a single crystal insulating film as a gate insulating film.

In recent years, it has become possible to form single-crystal insulating films of magnesia spinel (MgO.Al ₂ O ₃ ) on single-crystal silicon substrates. Since magnesia spinel has a specific dielectric constant of 8 to 9, which is about twice that of SiO ₂ 's 3.9, it is possible to increase the capacitance by using it for the gate insulating film of MIS type semiconductor devices. This has the advantage that the transfer conductance gm can be increased and the amount of charge stored in the dynamic memory can be increased.

However, since an electron capture level Nss of about 10 ¹³ cm ^-2 exists at the interface between the magnesia spinel film and the silicon substrate, good device characteristics cannot be obtained.
This means that the lattice constant of magnesia spinel is 8.02.
Å, 5.43Å for silicon, twice and 3 times each.
Although a single crystal insulating film has been realized because of matching with double the lattice length, there are many bonds that do not participate in covalent bonding at these bonding interfaces.

The present invention provides a novel structure that improves these drawbacks.
The purpose of the present invention is to provide a MIS type transistor, and the gist thereof is to provide a SiO ₂ film between a magnesia spinel film and a semiconductor substrate.

Hereinafter, a case where the present invention is applied to an MIS type transistor will be explained in detail, taking as an example.

FIG. 1 is a cross-sectional view illustrating the structure of an MIS transistor. In the figure, 1 is a semiconductor substrate, 2 is a single crystal insulating film, 3 is an insulating film serving as an oxidation-resistant mask,
4, 41, 42, 45, 47 are insulating films, 5 is the first
Reference numeral 6 indicates an ion flying direction, 61 an impurity region, 7 a contact hole, and 8 a second electrode.

An N-channel MIS transistor will be manufactured using silicon having P-type conductivity for the semiconductor substrate 1 and magnesia spinel for the single crystal insulating film 2, and the manufacturing process will be explained step by step.

First, a magnesia spinel film 2 is epitaxially grown on the surface of a silicon substrate 1 (FIG. 1a). Since the film is used as a gate insulating film, it is
The film is formed to a desired thickness within a range of about 1000 Å. The epitaxial growth is performed using H ₂ , HC,
This can be carried out by using CO ₂ gas and transporting Mg and A as chlorides.

Next, SiO ₂ is applied to the surface of the magnesia spinel film 2.
After sequentially providing the film 41, followed by the nitride film 3 and the SiO ₂ film 42, the SiO ₂ film 42 is selectively removed by normal photo etching to form a pattern, and then nitriding is performed using the SiO ₂ film pattern as a mask. The film 3, the SiO ₂ film 41, and the magnesia spinel film 2 are sequentially selectively removed (FIG. 1b).
The thickness of the SiO ₂ films 41 and 42 is approximately 100 to 500 Å.
The thickness of the nitride film 3 is preferably about 500 to 1000 Å.
As a means for providing the SiO ₂ film 41, a vapor phase growth method or a sputter deposition method is preferable.

Next, the SiO ₂ film 4 is formed by heat treatment in an oxygen atmosphere.
is formed (Fig. 1c). The SiO ₂ film 4 preferably has a thickness of about 0.5 to 1 micron because it is necessary for device isolation.

Next, after the SiO ₂ film 42, nitride film 3, and SiO ₂ film 41 are removed in sequence, they are removed by heat treatment in an oxidizing atmosphere.
A SiO ₂ film 45 is provided (FIG. 1d). SiO ₂ film 4
When removing 2 and 41, the surface of the SiO ₂ film 4 is also removed to some extent, but since the film is thick, the amount of reduction can be ignored.
A heated phosphoric acid solution is used to remove the nitride film 3, but this solution has the ability to etch magnesia spinel, and the SiO ₂ film 41 has the role of preventing this. In the SiO ₂ film 45, oxygen diffuses through the magnesia spinel film 2, and the silicon substrate 1
It is formed as a result of an amorphous SiO ₂ film on the surface. The SiO ₂ film 45 is provided to reduce the electron capture level at the interface between the magnesia spinel film 2 and the silicon substrate 1, and a film thickness of several tens to 100 angstroms is sufficient. The _SiO2
Although the thickness of the film 45 can be freely set to 100 Å or more, it is desirable that the capacitance of the gate insulating film is large in order to improve transistor characteristics, and for this purpose, a thick magnesia spinel film with a large specific dielectric constant is used. It is necessary.

Next, after a polycrystalline silicon film 5 is provided, a desired pattern is formed by a normal photoetching process (FIG. 1e). Since the polycrystalline silicon film 5 is used as an electrode, it is necessary to contain impurities, and such impurities may be introduced into the atmosphere during film formation, or may be carried out by thermal diffusion or ion implantation after film formation. The choice is free.

Next, an N-type impurity 6 such as phosphorus or arsenic is ion-implanted, followed by heat treatment to form an N-type impurity region 61 on the surface of the silicon substrate 1 (FIG. 1f).

Next, after an insulating film 47 is provided, a contact hole 7 is formed by a normal photo etching process (FIG. 1g).

Next, after a metal film 8 of aluminum or the like is provided, it is selectively removed by a photo etching process and the MIS
A transistor is formed (FIG. 1h).

FIG. 2 is a diagram illustrating another embodiment of forming a MIS transistor using the present invention. In the figure, the same symbols as in FIG. 1 indicate substances having the same functions, and 43 and 44 are insulating films.

An N-channel transistor will be manufactured using silicon for the semiconductor substrate 1 and magnesia spinel for the single crystal insulating film 2, and the manufacturing process will be explained step by step.

First, a SiO ₂ film 43 is placed on the surface of the silicon substrate 1.
Subsequently, a nitride film 3 and a SiO ₂ film 44 are sequentially provided (FIG. 2a).

Next, by normal photoetching process
The SiO ₂ film 44 is selectively removed to form a desired pattern, and then the nitride film 3 and the SiO ₂ film 43 are sequentially selectively removed using the pattern as a mask (FIG. 2b).

Next, a thick SiO ₂ film 4 for element isolation is formed by heat treatment in an oxidizing atmosphere (FIG. 2c).

Next, the SiO ₂ film 44, the nitride film 3, and the SiO ₂ film 43 are sequentially removed to expose a part of the surface of the silicon substrate 1, and then the magnesia spinel film 2 is epitaxially grown (see FIG. 2). d).

The epitaxial growth is performed on the exposed surface of the silicon substrate 1, but the SiO ₂ film 4
Even if it is a polycrystalline film, it is not formed on the surface. The inventor believes that this is because the magnesia spinel on SiO ₂ is etched by the action of HC gas in the epitaxial growth atmosphere.

After this structure is formed, heat treatment in an oxidizing atmosphere results in the same structure as in Figure 1d, and hereafter referred to as Figure 1.
The MIS transistor is formed in the same way as shown in the figure.

According to the present invention, the interface state is formed in the gate insulating film.
It is clear that MIS transistor characteristics can be improved because it can be made to be almost the same as a conventional MIS transistor using SiO ₂ and the gate capacitance can be increased.

Furthermore, if the present invention is applied to the MIS capacitor of a dynamic memory, the accumulated charge density can be increased, so soft errors caused by α rays can be reduced, and the pattern size can be reduced to improve the integration density.

In the above description, magnesia spinel is grown in a vapor phase on a silicon substrate, but the present invention can also be applied to a case in which sapphire is grown in a vapor phase.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention, and FIG. 2 is a diagram for explaining another embodiment, showing a cross section of a semiconductor device in each process diagram. In the figure, 1 is a semiconductor substrate, 2 is a single crystal insulating film, 3 is an insulating film, 4, 41, 42, 43, 44, 45, 47
is an insulating film, 5 is an electrode, 6 is an ion flying direction, 6
1 is an impurity region, 7 is a contact hole, and 8 is an electrode.

Claims (1)

[Claims] 1. A gate insulating film of an MIS transistor provided on a semiconductor substrate includes an amorphous insulating film provided on the semiconductor substrate and a single crystal provided on the amorphous insulating film. A semiconductor device comprising a laminated film including an insulating film. 2 The semiconductor substrate is silicon and the amorphous insulating film is
2. The semiconductor device according to item 1, wherein the SiO ₂ single crystal insulating film is magnesia spinel or saphire.