JPS5924426B2 - Kanji pattern storage device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a kanji pattern storage device.

In recent years, Japanese language processing using electronic computer systems has become popular.

In order to perform Japanese processing, a kanji pattern storage device is used to output Japanese sentences including kanji. The Kanji character l is expressed by a dot matrix of 16×18, 24×24, or 32×32 dots. For example, to represent 3,000 characters of Kanji, graphic symbols, etc. using a 16×18 dot matrix per character, a storage capacity of 864,000 bits is required. Using a larger dot matrix makes the glyphs more beautiful and easier to read, but this naturally requires a larger storage capacity. When printing Japanese text by connecting a terminal device such as a printer to a remote computer via a telephone line, it is necessary to memorize the kanji patterns in the terminal device in order to reduce the amount of information transmitted over the telephone line. It is desirable to have it built-in.

Currently, integrated circuits for storing kanji patterns are being developed in order to reduce the cost of terminal devices. Due to the rapid progress of integrated circuit technology, in the near future, a memory element with a storage capacity of about 3,000 characters (approximately 1 million bits) will be realized within an l element.
In such a case, if a very small number of defective bits were allowed to exist inside a storage element with a storage capacity of one million bits, the yield of the storage element would be greatly improved. One object of the present invention is to increase the capacity by allowing the use of a large-capacity storage element that stores data of defective characters of several crosses, that is, several percent of the total number of stored characters of several thousand characters. Improving the yield of memory elements, resulting in
The object of the present invention is to provide an inexpensive kanji pattern storage device.

Another object of the present invention is to reduce the cost of a kanji pattern storage device by reducing the storage capacity of a spare storage element that stores correct character data corresponding to the defective character data.

Still another object of the present invention is to shorten the time required to rewrite defective character data continued from the large-capacity storage element with spare character data.

According to the present invention, which achieves the above objects, there is provided a kanji pattern storage element, a spare kanji pattern storage element that stores correct partial patterns only for defective portions of kanji patterns stored in the element, and kanji patterns including the defective portions. There is provided a kanji pattern storage device comprising output means for replacing the defective part with a correct partial pattern stored in the spare kanji pattern storage element when outputting the kanji pattern.

Further details of the present invention will be explained below using Examples. 1st
The figure is a block diagram of one embodiment of the present invention. Reference numeral 1 denotes a Kanji pattern memory element (hereinafter abbreviated as "KPM") having a storage capacity for the required amount, for example, about 3,000 characters.

Here, one character is represented by a 16 x 18 bit dot matrix. As KPM1, a read-only memory element in which character data is written using a photomask used during the manufacturing of the concentrator circuit, or an electrically written read-only memory element, etc. can be used. Here, KPM1 is allowed to include defective character data equivalent to several crosses. 2 is a buffer memory that can be read and written.

The buffer memory 2 typically has a storage capacity for one character to several hundred characters, but the storage capacity generally varies depending on the type of printer, cathode ray tube display, or other terminal device. Reference numeral 3 denotes an electrically writable field programmable logic array (hereinafter abbreviated as "FPLA"), and this EPLA has an AND generator and an OR generator inside.

Regarding PLA, see DR. WiIIIamN. Carr
Others ゜“MOS/LSIDesignandAppIi
It is known from chapter 8 of catiOn and others. FPLA3
contains the address of the defective character contained in KPM1 and the address of correct character data to be stored in a spare Kanji pattern storage element corresponding to each defective character. Reference numeral 4 denotes a spare Kanji pattern memory element (hereinafter abbreviated as "SPM").

), and is specifically purchased as an electrically programmable read-only memory (EPROM), and has a storage capacity of several crosses. Inspection for defects in the KPM1 and writing in the EPLA3 and SPM4 in response to defects are performed using a processing device such as a minicomputer after the KPM1 is manufactured.

This processing device is equipped with a memory device such as a desk that stores the KPM test program, the correct data in the KPM, and the writing programs to the FPLA and SPM. Connected. This processing device specifies the character address of KPMl, reads the corresponding character data, compares it with the built-in correct character data, and if there is a defective character, stores the defective character address, the corresponding start address in the SPM, and the following information. FP the bad block address
Write to LA3 and at the same time write correct answer data to SPM4. Reference numeral 5 in FIG. 1 is a memory control circuit for controlling reading and writing of the buffer memory 2, SPM 4, and the like.

The control circuit 5 can be made by combining conventional logic elements, as will be explained in detail later, or can be made by using a microprocessor with a built-in program. 6 to 13 are signal lines.

A character address signal is input to the signal line 6. As an example of a character address, 1 determined by JIS-C6226
4-bit graphic character code and 0, 1, 2,
A binary code of about 12 bits assigned as 3... is used. Read data from KPMl is output to signal line 7. In this embodiment, the signal line 7 has a width of 16 bits. Therefore, in order to output one character, 16-bit width data is output to the signal line 7 18 times, and this data is sequentially written to the buffer 2. The character data stored in the buffer memory 2 is outputted to the signal line 8 in synchronization with the timing signal of the terminal device. The normal character data stored in KPM1 is output to the signal line 8 through the above-mentioned path. The character address signal is input to KPM1 and at the same time, it is also input to FPLA3 via signal line 6.

When a character address signal is input to FPLA3, FPL
A3 outputs 11-bit wide data in the format shown in FIG. However, FPLA3 outputs significant data only when a bad character in KPM1 is read. In FIG. 2, bits 0 to 7 indicate the start address on SPM4 of spare character data prepared for each defective character in KPM1,
This is output to signal line 9. In this example, KPMl
Defective character data of up to 256 characters included in SPM4
It can be replaced with the spare character data stored in . However, depending on the allocation to the mode section, which will be described later, and the storage capacity of the SPM4, there may be fewer than 256 defective characters that can be pre-selected. Bits 8 to 10 in Figure 2 are SPM
This is a mode section for identifying the state of spare character data for each defective character stored in the memory 4, and is output to the signal line 10.

The function of this mode section will be explained using FIGS. 3 and 4. FIG. 3 shows an example of a 16×18 dot matrix.

The sections marked with 1 in FIG. 3 represent the data "B", and the blank sections represent the data "0°". Third
In the example shown in the figure, the kanji character "A" is shown. KP in Figure 1
Ml reads character data to the signal line 7 in units of rows each consisting of 16 bits. In FIG. 3, "l" in the 14th row and 11th column and "0" in the 15th row and 10th column indicate the presence of defective bits that occur during the manufacturing process of the device. Such defective bits appear as extra black dots or partial missing characters when printed by a printer. Figure 4 is 16x18 as shown in Figure 3.
The dot matrix is divided into regions A to F. Bits 8 to 10 of the mode section in FIG. 2 can represent eight different numerical values from 0 to 7.

These numerical values 0 to 7 are associated with the blocks A to F shown in FIG. 4, for example, as follows. Memory control circuit 5 in FIG.
When all "O" are output on the signal line 10, KPMl
It is determined that a normal character has been output, and no special action is taken.

When 1 to 7 are output to the signal line 10, the memory control circuit 5 reads the character pattern in the area corresponding to the A-F block set for each mode from the SPM 4, and stores the corresponding memory in the buffer memory 2. It works by rewriting the contents of the location. To the signal line 12 is an address signal to the SPM4,
Address signals of the buffer memory 2 and the like are output to the signal line 13. Since the amount of data to be read from the SPM 4 differs depending on the mode, the storage control circuit 5 refers to the SPM start address output to the signal line 9 and the mode signal on the signal line 10 and reads the required number of address signals and SPM read start signal. occurs. The storage control circuit 5 starts up the SPM4,
The preliminary character data read from SPM4 is sent to signal line 1.
1 to the buffer memory 2. At this time, an address signal to the buffer memory 2 is sent from the memory control circuit 5 via the signal line 13. Bad character “A” shown in Figure 3
In this example, only 64 bits of the E-block need to be prepared as a spare in the SPM4. FIG. 5 is a block diagram of an embodiment of the buffer memory 2 in FIG. 1, in which 20 is a readable/writable memory, 21 is a write data selector, 22 is a write data register, 23 is a read/write control circuit, and 24 is an address selector. , 25 are address registers.

The write data selector 21 receives KPM read data (signal line 7) and SPM read data (signal line 11).
) is input, and one of the data is selected depending on the presence or absence of a character defect by a data selection signal (signal line 13a) from the storage control circuit 5, and is read into the write data register 22. A write address signal and an address selection signal from the storage control circuit 5 are connected to signal lines 13d and 1, respectively.
3c to the address selector 24, and the write address is read into the address register 25. A write command from the storage control circuit 5 is input to the read/write control circuit 23 via the signal line 13b, and the circuit 23 that receives this command issues a read/write command to the read/write memory 20. The character data written in the memory 20 in this manner is read onto the signal line 8 in accordance with a read command (signal line 15b) and a read address signal (signal line 15a) from the terminal device. FIG. 6 is a block diagram of an example of the memory control circuit 5 in FIG.
2 is an SPM address counter, 53 is a counter step control circuit, and 54 is a timing circuit.

The mode identification circuit 51 decodes the mode signal on the signal line 10, and the address generation/control circuit 50. The operations of the counter step control circuit 53 and the timing circuit 54 are controlled.
If the mode signal on the signal line 10 is all “0” indicating normal character reading from KPM1, the control circuit 50
To write normal characters from Ml to buffer memory 2,
The data selection signal and address selection signal explained in FIG.
The calculated write address signal and write command are sent to signal line 1.
3 to the buffer memory 2. When data related to the defective character is output on the signal line 10, the mode identification circuit 51 decodes it and tells the control circuit 50 which block of the defective character is to be corrected, and counts the number of times the corrected data is read from the SPM 4 as a counter. This is transmitted to the step control circuit 53. The control circuit 50 calculates the address of the buffer memory 2 based on the information from the mode identification circuit 51, and updates the address sent to the buffer memory 2 in synchronization with the SPM address counter 52. The SPM address counter 52 sets the SPM (start) address output on the signal line 9, and then increments the content address in synchronization with the signal from the counter increment control circuit 53. In order to perform the above-described operation, the control circuit 5 connects the signal line 14 as necessary.
Receives control signals from the host device via the . In this case, the host device should notify the control circuit 5 via the signal line 14 that the character address signal has been sent to the signal line 6, and should also stop sending the character address signal while correcting the defective character. A signal from the control circuit 5 indicating this is received via the signal line 14. Although the storage control circuit 5 shown in FIG. 6 is an example of a configuration in which conventional logic elements are combined, a microprocessor with a built-in program may be used instead.

As described above, according to the present invention, it is not necessary to prepare character data for all of the defective characters, thereby obtaining the advantage of reducing the storage capacity of the SPM 4.

It should be noted that it is possible to make a modification in which the mode part has more than 4 bits as shown in FIG. 2, and in addition to the example of division shown in FIG. -F
Various modifications can be made, such as dividing the program into sections (the entire program). FIG. 7 is a block diagram of another practical example of the present invention.

In FIG. 7, function blocks with the same reference numerals as in FIG. 1 are the same function blocks as in FIG. FPLA3″ in Figure 7 is SPM4 in FPLA3 in Figure 1.
The function of the memory control circuit 5'' in FIG. 7 is almost the same as that of the memory control circuit 5 in FIG. 1. In FIG. When input, KPM1, buffer memory 2 and memory control circuit 5'' operate in the same way as in the case of FIG.

When the character address input to signal line 6 specifies a defective character in KPMl, FPLA3''
Outputs a 4-bit signal. Pits O-7 in FIG. 8 are output to signal line 11 in FIG. 7, and bits 8-13 in FIG. 8 are output to signal line 20 in FIG. When the characters read from KPMl are normal, all bits 0 to 13 shown in Figure 8 are “
0''. At this time, the memory control circuit 5'' does not perform a preliminary character correction operation. The contents of bits 8 to 13 are O to 6.
It can take values up to 3, and these are assigned to 36 blocks of an 18x16 dot matrix as shown in FIG. That is, when a bad character in KPMl is read, the contents of bits 8-13 of the output of FPLA3'' are 14.
-31, 46-63. 63
, 62, 61, 60, . . . become 0, 1, 2, 3, . . . when complemented in base 64.

Bits O-7 in FIG. 8 represent preliminary character data for the block shown in bits 8-13.

The memory control circuit 5'' refers to the block name outputted to the signal line 20, outputs an address signal etc. to the signal line 13, and stores the spare character data outputted on the signal line 11 in the corresponding buffer memory 2. Write to the memory location. FPLA like this
3' includes in one circuit element a spare Kanji character pattern storage element and a means for storing the correspondence between a defective character address and an address of correct character data on the spare Kanji pattern storage element. Further, in FIG. 8, the bit width of the preliminary character data can be set to an arbitrary number of bits. In FIG. 7, if an FPLA3'' having a built-in register consisting of a flip-flop is used, one input defective character address signal is corrected in the FPLA3I and returned several times, thereby generating data in the format shown in FIG. A number equal to the number of feedbacks described above can be output to signal lines 11 and 20 in FIG.

That is, it is also possible to correct a character containing multiple defective blocks using correct data from the multiple blocks.
Although the case where a character is formed using a set of dots has been described above, it is clear from the gist of the present invention that the present invention can also be applied to a case where a character is formed using a set of vectors. As explained in detail above, the present invention, which has a reserve for defective characters, allows the presence of a certain amount of defective characters in a large-capacity kanji pattern storage element, which makes it difficult to manufacture this type of device. Yields can be increased and costs can be reduced.

Furthermore, in the present invention, only a partial pattern of each defective character is stored without storing the entirety as a spare, so a low-cost device with a small storage capacity can be realized. Further, according to the present invention, since the operation for correcting a defective character is started almost simultaneously (within several microseconds) with the start of reading out the defective character, extremely high-speed operation is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIGS. 2 to 4 are conceptual diagrams for explaining the operation of FIG. 1, and FIG.
6 is a block diagram of one embodiment of the buffer memory 2 and memory control circuit 5 of FIG. 1, FIG. 7 is a block diagram of another embodiment of the present invention, and FIGS. It is a conceptual diagram for explaining the operation of the figure. 1...Kanji pattern memory element (KPM), 2.
...Buffer memory, 3,3''...Field programmable logic array (FPLA), 4.
．． ．．・．． ．． Spare Kanji Pattern Memory Element (SPM), 5
, 5″... Memory control circuit, 6-15, 20...
····Signal line.

Claims (1)

[Claims] 1. A kanji pattern storage element, a spare kanji pattern storage element that stores correct partial patterns only for defective parts of the kanji pattern stored in the element, and a kanji pattern storage element that stores correct partial patterns only for defective parts of the kanji pattern stored in the element; A kanji pattern storage device comprising an output means for replacing the defective portion with a correct partial pattern stored in the kanji pattern storage device.