JPS5924464B2 - electronic display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic display device equipped with a display section for displaying numbers or characters, and more particularly to an electronic display device with improved power supply system for driving the display section and circuits. .

A device equipped with a display unit, hereinafter referred to as an electronic desktop calculator (hereinafter simply referred to as a calculator).

) will be explained using an example. FIG. 1 shows an example of the basic configuration of a calculator along with the flow of signals.

Signals specifying numbers and various calculation commands necessary for performing a desired calculation are applied to the input unit 1. This signal is sent to the control section 2 and register 3. The register 3 stores the number corresponding to the sent number signal. The contents stored in the register 3 are sequentially changed as the calculation progresses. The display section 4 performs a predetermined display corresponding to the information stored in the register. Further, the control section 2 decodes the signal from the input section 1 and then sends a predetermined signal to the memory 5 and the calculation section 6. In the memory 5, information is stored in accordance with the sent signal, and in response to this signal, information already stored is read out and sent to the calculation section 6. The arithmetic unit 6 performs predetermined arithmetic operations based on signals from the control unit 2 and the memory 5 and sends the results to the register 3. Register 3 stores this result. This result is memory 5
It may also be sent and stored. Then, the display section 4 performs a predetermined display according to the contents stored in the register 3. The control section 2 also includes a circuit that generates clock pulses. This clock pulse is commonly sent to the arithmetic unit 6, register 3, and display unit 4 to synchronize them. FIG. 2 shows an example of a conventional drive power supply system for a calculator having the above configuration. The power supply T has two terminals 8, 9
There is. The terminal 8 is connected to the display section 4 and the input section 1, and supplies power at a relatively high voltage V2 to each of them. The terminal 9 is connected to the control section 2, the memory 5, the arithmetic section 6, and the register 3, and supplies power to each of them with a voltage V1 lower than the voltage V2. A fluorescent display tube, liquid crystal, etc. is used for the display section, and the other control section 2, memory 5, calculation section 6,
When a circuit such as the resistor 3 is formed on a semiconductor substrate, the voltage V2 is usually two to three times higher than the voltage V1. That is, the voltage required to display using the above-mentioned materials is generally about two to three times higher than the voltage required to operate a circuit formed on a semiconductor substrate. For this reason, two types of voltage power supplies are used. For example, the minimum voltage necessary to display using a fluorescent display tube is about 25 V, and when a liquid crystal is used, a minimum voltage of about 15 V is required. In comparison, the voltage required to operate the circuit formed on the semiconductor substrate is approximately 8V. However, if it is 8V or more but up to about 30V, it will normally operate normally. However, in order to save power consumption, it is normally driven at about 8V. Further, a power source having the same voltage as the voltage applied to the display section 4 is applied to the input section 1 .

This is because the pulse train applied when driving the display section 4 is also applied to the input section 1 when performing dynamic display. This simplifies the circuit because there is no need to provide a special circuit for generating the pulse train used in the input section 1.
Next, read-only memory (hereinafter abbreviated as ROM) is mainly used in the conventional control unit 2.

). Figure 4 shows a ROM based on 0R logic.
is shown.

Terminals 11 and 12 are input terminals, and input signals 11 and 12
is applied. N-channel MOS field effect transistors (hereinafter referred to as FETs) 13 to 20 are 0
This is a switching FET that performs n-0ff operation. Corresponding to this operation, outputs are provided to the terminals 21-24. Similarly, N channel FETs 25 to 32 are 0n-0f.
This is a switching FET that performs 'f operation. terminal 33
-37 are output terminals to which output signals 01, 02, 03, 04, and 05 are received. Further, FETs 38 to 46 are used as loads, and terminals 47 and 48 are connected to the power supply voltage V1.
is the terminal to which is applied. Next, the operation of this circuit will be explained. Connect FETs l3 and l4 to input terminal 11 at 0f
It is assumed that a voltage is applied that causes the FETs to be in the f state, and a signal is applied to the input terminal 12 that causes the FETs 15 and 18 to be in the 0ff state. This signal causes the FETs 13 and 14 and the FETs 15 and 18 to become 0ff. Then, the voltage level of the terminal 21 changes to the same voltage level as the power supply voltage V1. Therefore, the FETs 25 and 27 are brought into the On state, and the voltage levels of the output terminals 34 and 36 change from the voltage level of V1 to a voltage level that is approximately the same as the ground voltage. When such a circuit is actually formed on a semiconductor substrate, FETs 13 to 20 for switching and FETs 25 to 32, and FETs for load
It is necessary to provide a predetermined resistance ratio with ET38-46.

That is, the resistance of the switching FETf)0n needs to be sufficiently smaller than the resistance of the load FET. This is because when the switching FET is in the On state, it is desired that the output level determined by the resistance ratio of the On resistance of the load FET and the switching FET be as close to the ground voltage as possible. One method for achieving such a resistance ratio is to make the width of the region where the channel of the switching FET is formed sufficiently larger than the distance between the source and drain. However, with this method, the entire ROM occupied area inevitably increases. Furthermore, if a ROM is designed using 0R logic, it is necessary to provide one ground line between each output line, which also increases the occupied area.

If the area occupied becomes large, it may become impossible to form a circuit on a single semiconductor substrate, or even if it is possible to form a circuit, the large area will reduce yields and increase manufacturing costs. Defects arise.

The above circuit describes a circuit that takes five outputs for two inputs.

However, in reality, the number of input and output lines is usually about 8 inputs and 24 outputs, respectively, and the above drawback becomes more problematic as the number of input and output lines increases. That is, as the number of input and output lines increases, the number of elements and the number of wirings also increase significantly. In order to eliminate the above-mentioned drawbacks, the present invention configures a ROM in high density using AND logic, and drives the circuit with a relatively high voltage power source used for the display section as its power source. It is an object of the present invention to provide an electronic display device with good reliability and high logic speed.

FIG. 3 shows a block diagram of an embodiment of the present invention.

As shown in this figure, the power supply to the control unit 2 includes a voltage V2.
Two power supplies are used: one with a voltage V1 and the other with a voltage V1. In other words, to operate the ROM circuit, a relatively high voltage power supply is used, and to operate the circuits that generate clock pulses, a relatively low voltage power supply is used to save power consumption. There is. This ROM
The power supply used for this is about two to three times more expensive than the power supply used to operate normal circuits. Supplying a high voltage to the control section 2 in this manner is very effective as will be explained below when the ROM of the control section 2 is configured with AND logic as shown in FIG. Next, AND which is an embodiment of the present invention
A ROM circuit based on logic will be explained. The high level and low level of the input/output waveform in this circuit correspond to the low level and high level of the human output waveform in FIG. First, the configuration of this circuit will be explained.

The terminals 55 and 56 are input terminals to which the human power signals 11 and 12 are applied. FETs 57-64 are set to 0 according to the input signal.
N-channel switching FE with n-0ff operation
It is T. This operation changes the voltage levels at terminals 65-68. Further, FETs 69 to 76 are the above-mentioned FETs.
This is an N-channel switching FET that performs 0n-0ff operation similarly to . Terminals 77-81 are output terminals. The terminals 82 and 83 are terminals to which a voltage V2 having the same voltage level as the power supply used for display is applied. FET84-92 are
This is a load FET, and clock pulses φ, , φ2 are applied to its gate. Terminals 93-96 are the terminals to which the clock pulses are applied. Next, the operation of this circuit will be described.

First, the waveforms of clock pulses φ2 and φ1 are shown in FIG. When the voltage level of φ2 is V2, terminals 65~
This is when the capacitance between the wiring path including 68 and the substrate is charged with electric charge. The operating region is when the voltage is at the ground voltage level. When the voltage level of φ2 is 2, the load F
Since ET84 to 87 are in the 0n state, terminals 65 to 68
An electric charge is charged to the capacitance between the wiring path containing the wiring path and the substrate.

When the voltage level of φ2 reaches the ground voltage level, a predetermined FET among the switching FETs 57 to 64 enters the On state according to the signals applied to the input terminals 55 and 56. As a result, the voltage level of any one of the wiring paths including terminals 65 to 68 changes to the ground voltage level. This is because a discharge path is formed between any one of the terminals 65 to 68 and the terminal 93 via the FET in the On state, and the stored charge is discharged to the terminal 93. For example, if signals 11 and 12 shown in FIG. 6 are applied, waveforms shown as A-D are applied to terminals 65-68, respectively. Also, terminal 65
Depending on the state of ~68, switching FET69~76
becomes 0n state or 0ff state. Hello, output terminal 7
If all the FETs between the wiring path including terminals 7 to 81 and the wiring path including terminal 95 are in the On state, a discharge path is formed between them. When the discharge path is formed, the voltage level at the output terminal becomes the ground voltage level, and if the discharge path is not formed, the voltage level at the output terminal is maintained at the same voltage level as the power supply voltage. At this time, similarly to the above, when the voltage level of φ1 is V2, it is the time when the wiring path including the output terminals 77 to 81 is charged with electric charge, and when it is at the ground voltage level, it is the operating region. The output waveform corresponding to the voltage waveform of the terminals 65 to 68 is, for example, a waveform as shown in FIG. In this embodiment, there are 2 inputs and 5 outputs, but the number of inputs and outputs of a ROM used in a calculator or the like is generally about 8 inputs and 24 outputs, respectively.

With the above configuration, the load FET and the switching FET do not need to have a specific resistance ratio as in the circuit shown in FIG. 4, and may be configured with exactly the same FET.

This is because for both the load ET and the switching FET, only the 0n-0ff operation is a problem, and the resistance ratio etc. are not a problem. This indicates that when a circuit is formed on a semiconductor substrate, the area occupied by the FET can be minimized. Therefore, the area occupied by the ROM is greatly reduced. At the same time, there is no need to provide a grounding wire between the output lines, which reduces the occupied area. This is particularly effective when a system is being extensively modified.
In other words, the degree of integration within one semiconductor substrate can be increased,
Yield and reliability are improved. In this circuit, the characteristics during discharging or charging are determined by the product of the capacitance between the wiring path and the substrate, the resistance of the wiring section, and the On resistance of the FET.

This indicates that when the number of switching FETs connected in series increases and the resistance of this portion increases, the time required to reach the operating voltage becomes longer. For this reason, when using the same low voltage power source as the drive power source that drives the circuit formed on the semiconductor substrate as in the past, it is necessary to ensure that the pulse width of the clock pulses φ1 and φ2 is sufficient to prevent malfunctions. Must be. Therefore, the calculation time becomes extremely long. Furthermore, if the time required to reach the operating voltage is long, it may cause malfunction when operating the next stage circuit, etc., resulting in a decrease in reliability. For these reasons, in the past, the number of input and output lines was inevitably limited, making it difficult to scale up the system. However, as in the present invention, the voltage V1, which has been used conventionally as an operating power supply, is
If a power supply with a voltage V2 that is about three times higher is used, the above drawbacks can be overcome with a slight sacrifice in power consumption.

That is, by increasing the rate of rise to the operating voltage, malfunctions will not occur even if the width of the clock pulse is small. Therefore, the time required for calculation can be shortened. D. According to the present invention, the power source used for display is used as the high voltage power source, so there is no need to provide a separate high voltage power source. In order to generate clock pulses of φ1 and φ2, the circuit shown in FIG. 7 may be used.

vinegar ! That is, if a clock pulse of voltage V1 is applied to the input terminal 101 and the FETlO2 is operated from 0n to 0ff, a clock pulse of voltage 2 corresponding to the input clock pulse is outputted to the output terminal 103. In addition, FETlO
4 is a depletion FET serving as a load. Further, the terminal 105 is a power supply voltage application terminal to which the voltage V2 is applied. The present invention can be applied not only to the calculator shown in the embodiment, but also to an electronic display device equipped with a general display section.

Further, although a clocked circuit is used in the ROM embodiment, the present invention can also be applied to a ROM using ordinary AND logic. In the embodiment, RO is controlled by an N-channel FET.
Although M is configured, it goes without saying that it may be configured with a P channel FET.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the signal system for a calculator.

Claims (1)

[Claims] 1. An input section to which a signal is applied, an arithmetic section that decodes this signal and outputs a predetermined output signal, a display section that displays a predetermined display in response to the output signal from the arithmetic section, and the arithmetic section. and a control section that controls the display section; and a power source that has at least two types of voltages and supplies predetermined voltages to the input section, the calculation section, the display section, and the control section. What is claimed is: 1. An electronic display device comprising a ROM formed by connecting EETs in series, and driven by a higher voltage of the power source.