JPS5925437B2 - remote multiplex controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a remote multiplex control device using a time division multiplex transmission system.

An object of the present invention is to enable mutual control between any two terminals among a large number of terminals installed on a dedicated two-core wire extended from a central control panel, and to The purpose of this invention is to make it possible to configure a pair of terminal devices that can control a set of objects.

The present invention will be explained in detail below with reference to Examples.

FIG. 1 is a basic circuit diagram of the remote multiplexing device of the present invention, which consists of one central control panel 1 and a plurality of terminal devices 2 with non-polar connection using a dedicated two-core wire 3. A cyclic time-division multiplex transmission system is used to allow them to work independently. In this system, an address is given to each terminal device 2 by the address switch 4 of each terminal device 2, and the central control panel 1 and each terminal device 2 sequentially transmit and receive pulse signals cyclically. In addition, non-polarization is achieved by adopting a bipolar symmetrical pulse method. On the dedicated two-core wire 3, there is a second
As shown in FIG. a, an initial signal P1, an address signal P2, a control signal P3 and a return signal standby signal P4 are transmitted from the central control panel 1, and a return signal is transmitted from the terminal device 2. The terminal device 2 whose rear address matches is selected by the address signal P2, and the load switching contact 5 of the terminal device 2 is controlled by the control signal P3. Then, the return signal causes the terminal device 2 to return the data input to the control input switch 6 of the terminal device 2 with the matching address to the central control panel 1. Here, the return signal is transmitted in current mode, and the others are transmitted in voltage mode. As shown in Fig. 3, the central control panel 1 includes a power supply circuit 7 and a signal generation circuit 8.
The coupling circuit 9 drives the OV, 5V symmetrical pulse signals sent from the signal generation circuit 8 into -24V, +24V bipolar symmetrical pulses, and also sends the signals returned from the terminal device 2. The signal is detected and sent to the signal generation circuit 8.

The signal generation circuit 8 is a memory (RAM) as shown in FIG.
10, address counter 11, first shift register 1
The output of the address counter 11 and the data in the memory 10 are sent to the coupling circuit 9 as a signal output via the first shift register 12, and conversely, the terminal device 2 detected by the coupling circuit 9 The return signal from the second shift register 13 is written into the memory 10 via the second shift register 13. The output of the address counter 11 is
and the address of memory 10 are determined. At this time, the gate 14 inputs the exclusive OR of the n-th bit of the output of the address counter 11 and the read/write signal R/W of the memory 10 to the n-th bit of the address of the memory 10. Note that the first shift register 12 is a parallel input, serial output shift register, and the second shift register 13 is a serial input, parallel output shift register.
Further, FIG. 2b shows a read signal of the memory 10, and FIG. 2c shows a write signal. Terminal 2 is dedicated 2 as shown in Figure 5.
The pulse signal input from the core wire 3 is converted into a voltage of 0 to 5 V by the terminal coupling circuit 15, and then is converted to a voltage of 0 to 5 V by the terminal coupling circuit 15.
The pulse width is determined by , and a signal of 1 or O is sent to the shift register 17 .

This shift register 17 is a shift register with serial input and parallel output, and the parallel address signal output from this shift register 17 is judged by an address comparison circuit 18 to see if it matches the address switch 4, and if it matches, a relay is sent. A control signal is sent to the drive circuit 19. Further, the control input is generated into a return signal by the pulse width determining circuit 16 in the return signal forming circuit 20, and is sent to the terminal coupling circuit 15.
It is transmitted as a return signal from the dedicated two-core wire 3. Now, if the output of the address counter 11 is X (the nth bit is O
), the return signal from the terminal device 2 at address X is written to address X in the memory 10.

Here, when the R/W signal is O, it is a write state, and when it is 1, it is a read state. Next, when data is read from the memory 10 in order to send a ram signal, the R/W signal becomes 1, and the n-th bit of the address of the memory 10 is inverted by the gate 14. Therefore, memory 10
The data at address X+2n-1 is read out and sent as a control signal to the terminal device 2 at address X. Also, on the contrary, the output of the address counter 11 is X+2n-! (The n-th bit is 1), the return signal from the terminal device 2 at address x+2n-1 is written to address X+2n-1 of memory 10, and when reading the data at address The signal is sent as a control signal for the terminal device 2 of the first terminal device 2. In this way, the terminal device 2 at address X and the terminal device 2 at address X+2n-1 can control each other. As described above, the present invention includes an address counter that outputs binary address data consisting of a plurality of bits into a signal generation circuit in a central control panel, and whose output changes sequentially in a cyclical manner.
A memory is provided to store the control signal to be sent to each terminal device and the return signal sent from each terminal device for each address, and the output of the address counter is sent as the address signal of the terminal device and is also used as the address input of the memory. and the output of the n-th bit, which is the bit corresponding to any one of the outputs of the address counter, to the n-th input, which is any one bit, among the address inputs of the memory; Between a terminal device having an address x where the nth bit is 0 and an exclusive OR operation output with the memory read/write signal is input, and a terminal device having an address X+2n-1 where the nth bit is 1. Since the return signal from one side becomes the control signal from the other, any one of the multiple terminals installed on the signal line, such as a dedicated 2-core line extended from the central control panel, It is possible to control each other between any two sets of terminals having addresses that differ only in the n-th bit, and it is also possible to configure many pairs of terminals that can be controlled. be.

[Brief explanation of the drawing]

Fig. 1 is a basic circuit diagram of an embodiment of the remote multiplex control device of the present invention, Figs. 2 a to c are main signal waveform diagrams of the above, Fig. 3 is a circuit diagram of the central control panel of the above, and Fig. 4 is a circuit diagram of the signal generating circuit same as above, and FIG. 5 is a circuit diagram of the terminal device same as above. 1... Central leg control board, 2... Terminal, 8
......Signal generation circuit, 10...Memory, 11...Address counter 14...
...Exclusive OR gate.

Claims (1)

[Claims] 1. In a remote multiplex control device that transmits pulse signals between one central control panel and a plurality of terminal devices using a cyclic time division multiplex transmission method, a 2 An address counter that outputs address data in base numbers and whose output changes cyclically in sequence, and a memory that stores control signals to be sent to each terminal device and return signals sent from each terminal device for each address. , the output of the address counter is sent as the address signal of the terminal device and inputted into the address input of the memory, and the output of the address counter is inputted to the n-th input of any one bit among the address inputs of the memory. Input the output of the n-th bit corresponding to any one of the above bits and the exclusive OR operation output of the memory read/write signal,
A terminal device having an address x whose nth bit is 0, and n
A remote multiplex control device characterized in that it is configured to communicate with a terminal having an address x+2^n^-^1 whose bit is 1 so that a return signal of one becomes a control signal of the other.