JPS5927490B2 - integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit having a divide-by-9 function.

Generally, integrated circuits are limited in the number of terminals (pins) on a package, and the number of terminals cannot be increased freely, so even if there are functions that one would like to incorporate into an integrated circuit, it may not be possible to incorporate all of them.

The present invention provides an integrated circuit that compensates for such disadvantages unique to integrated circuits and is designed to effectively utilize the terminals of the integrated circuit to provide more functions within the integrated circuit.

Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining its operation.

In FIG. 1, transistor Q1. Q2. Q3゜Q4
'Q5 and resistors R2, R3, R4t R5t Re and current source ■1. I2. Circuit 1 surrounded by a dashed line is a frequency dividing circuit consisting of a well-known T-type flip-flop circuit, and when a voltage as shown in Figure 2a is applied to terminal T1, 1/ as shown in Figure 2 at T3.
It outputs a waveform whose frequency is divided by two.

Further, by connecting a transistor Q6 constituting a control circuit in parallel with the transistor Q2, the operation of the circuit 1, and thus the T-type flip-flop circuit, is controlled.

That is, when the transistor Q6 is cut off, the circuit 1 performs a flip-flop operation, and thus performs a frequency division operation, but when the transistor Q6 is turned on, the transistor Q
The circuit consisting of 2 to Q5, resistors R3 to R6, and current sources 11 to
When a voltage as shown in Fig. 2a is applied to terminal T
3, a voltage having a waveform as shown in FIG. 2C having the same repetition period as the voltage in FIG. 2a is outputted.

That is, the circuit 1 in FIG. 1 cuts off the transistor Q6,
Due to conduction, it is controlled to have two states: whether or not the frequency dividing operation is performed.

Furthermore, in the embodiment shown in FIG. 1, the output point of the differentiating circuit consisting of the capacitor C and the resistor R7 is connected to the terminal T21, and the DC bias voltage of the differentiating circuit is connected to the ground and the power supply (2) by the switch S.

0.

Further, the terminal T2' is connected to the (g) input terminal of the comparator CO0, the (c) input terminal of the comparator CO2, and the (g) input terminal of the comparator CO3, and the other input terminals of the comparators CO1, CO2 and CO3 are respectively referenced. A voltage v1° (Vcc V2 ) t V3 is given, and the magnitude of the opening of these reference voltages is (VOOV
2)>Vl>V3.

The output terminal of the comparator CO1 is connected to the transistor Q6 via the resistor R1.

Further, the outputs of the comparators CO2 and C03 are respectively input to an AND circuit A, and the output terminal of the AND circuit A is connected to a terminal T4.

The first circuit includes the comparators CO2 and C03 and the AND circuit A. The circuit surrounded by a dotted line in the figure sets the voltage of the terminal T4 to a high level when the voltage V T 2' of the terminal T2 is ■3〈■T2'〈■cc-■2, and also
The pulse signal processing circuit 2 functions to set the terminal T4 to a low level when the voltage at the terminal T4 is in a range other than the above range.

Here, when a rectangular wave signal as shown in Fig. 3a, whose amplitude is smaller than 1/2 vcc and larger than the voltage v2°v3, is input to the terminal T2, the switch S is connected to the ground side. When the signal is present, a signal (differential pulse) having a waveform as shown in FIG. 3 appears at the terminal T2'.

In this case, the reference voltage ■1 of comparator CO1 is 1/2
If VOO is selected, the voltage waveform appearing at the terminal T2' is a pulse-like one whose peak value is smaller than 1/2 Vcc centered around the ground, so the voltage at the terminal T2 is always smaller than 1.

Therefore, the output of the comparator CO1 is always at the roll level, so the transistor Q6 is in a cut-off state, and the circuit 1 surrounded by the dashed line in FIG. 1 operates as a T-type flip-flop circuit.

Furthermore, the pulse signal processing circuit 2 is configured so that the voltage at the terminal T2' is
In order to set the terminal T4 to a high level when the voltage exceeds 3, a pulse as shown in FIG. 3C is outputted to the terminal T4.

In addition, when the switch S is connected to the power supply VOO side, the terminal T2' has a voltage V as shown in FIG. 3d.

A waveform voltage with pulses superimposed around 0 appears.

The amplitude of the input signal to terminal T2 is set to be smaller than 1/2vcc and larger than the thickness of voltage ■2,
The peak value of the pulse voltage waveform appearing at terminal T2' is also 1/2
■Smaller than cc.

Therefore, the voltage waveform appearing at terminal T2' is always 1/2V
If the voltage of vl is higher than OO and is set as V1=1/2VOO, the voltage of T2' will always be higher than the comparator reference voltage v1, and the output of comparator C01 will always be at a high level. Transistor Q
Add up 6.

Therefore, the circuit 1 surrounded by the dashed line in FIG. 1 does not perform frequency dividing operation to function as a T-type flip-flop circuit.

In addition, the pulse signal processing circuit 2 surrounded by a dotted line in FIG.
4, a voltage having a waveform as shown in FIG. 3e is output to the terminal T4.

That is, as is clear from the above explanation, the DC bias voltage of the differentiating circuit composed of the capacitor C and the resistor R7 is grounded or the power supply voltage ■.

Depending on whether it is set to 0, the output of the pulse signal processing circuit 2 will be as shown in C and e in FIG.

They are only out of phase and voltage v2. ■３
If you make them equal, the period and pulse width will remain exactly the same.

On the other hand, it is clear that in the circuit 1 surrounded by the dashed line in FIG. 1, switching is performed as to whether or not to divide the frequency.

Therefore, the terminal T2 can be used as a pulse input terminal for frequency information, and depending on the change in the DC bias voltage appearing on the terminal T2, the circuit 1 inside the integrated circuit can be put into a state where the frequency division operation is performed or a state where the frequency division operation is not performed. It can be used as a terminal that can be selectively set.

Next, a case will be described in which this embodiment, which performs the above operations, is applied to, for example, a rotation control circuit for a motor that drives a record player that rotates at a constant rotation speed.

In FIG. 1, a frequency generator (hereinafter referred to as
FG) is applied, and a reference pulse signal of a constant frequency is applied to the terminal T2.

The signal applied to terminal T1 is transferred by circuit 1 to switch S
is connected to the ground side, the frequency is divided and switch S is connected to V
As described above, when connected to the OO side, the frequency is not divided but the phase is inverted and outputted to the terminal T3.

Further, the reference pulse signal applied to the terminal T2 is outputted to the terminal T4 at the same frequency via the pulse signal processing circuit 2.

The motor that drives the record player maintains its constant rotational performance by being supplied with a current proportional to the phase difference between the reference pulse signal appearing at terminal T4 and the motor rotation information signal appearing at terminal T3.

At this time, while the record player is rotating at a constant speed, the signal frequencies at the terminals T3 and T4 are the same.

The following characteristics occur depending on whether the switch S is connected to either ground or CC, that is, whether the circuit 1 performs frequency division operation or not.

■ When switch S is on the ground side, that is, when circuit 1 performs frequency dividing operation, the number of detections to generate a phase difference is reduced to 1/2 compared to the signal frequency of terminal T1, so the response of the motor becomes slightly worse. .

However, on the other hand, the maximum error phase for the phase shift is F
The dynamic range of phase error detection can be increased because it can be increased by up to two periods of the G output signal.

■ When switch S is set to VCCIlIl, that is, when circuit 1 does not perform frequency dividing operation, the number of detections to generate a phase difference is equal to the signal frequency of terminal T1, and phase errors can be detected quickly, resulting in good motor response. Become.

However, on the other hand, the maximum width of the phase error is as small as one period of the FG output signal.

That is, depending on whether the switch S is set to the ground side or to the VOO side, it is possible to select whether to use the phase error detection dynamic range or the motor response.

Which of the above two characteristics is selected often differs depending on the motor or device to be controlled.

However, according to the present invention, the above two characteristics can be selected without increasing the number of terminals.

As described above, the present invention makes it possible to input different types of information by applying a DC bias voltage and a pulse signal in a superimposed manner to one terminal (corresponding to T2' in the embodiment of FIG. 1). It is possible to realize an integrated circuit without increasing the number of terminals, and it has a great effect on realizing higher integration, higher functionality, and generalization of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2a is a circuit diagram of an embodiment of the present invention. b, c and FIGS. 3a, b, c, d, and e are signal waveform diagrams of each part in FIG. 1. 1... Circuit, 2... Pulse signal processing circuit, T1°T2', T3. T4...terminal,
Qll Q2 j Q3j Q4 jQ5. Q6...
・・・Transistor, COl, CO2, CO3...
... Comparator, A ... Ant circuit, ■1
．． V2゜■3...Reference voltage, VOO...
·Power-supply voltage.

Claims (1)

[Claims] 1. A circuit capable of performing a frequency division operation, and a hanging circuit that performs the frequency division operation in response to switching of a DC bias voltage, and is set to either a frequency division operation state or a non-frequency division operation state. a control circuit including a trailing bias switching circuit; and a pulse signal processing circuit having an input section connected to one terminal of the bias switching circuit, performing the frequency division operation and performing pulse signal processing unrelated to the input signal to the trailing circuit. , an input circuit for supplying a pulse signal to be input to the pulse signal processing circuit to one terminal of the bias switching circuit, and a pulse signal superimposed on the DC bias voltage is connected to one terminal of the bias switching circuit. The control circuit is configured to input the input terminal to the input terminal of the pulse signal processing circuit connected to the terminal, and the control circuit divides the frequency of the circuit capable of performing the frequency division operation according to the DC bias voltage set by the bias switching circuit. In addition, the pulse signal processing circuit is configured to process the pulse signal regardless of the setting of the DC bias voltage, and the pulse signal processing circuit is configured to process the pulse signal regardless of the setting of the DC bias voltage, and can select whether the frequency division operation state or the non-frequency division operation state is selected from one input terminal. An integrated circuit characterized in that it is possible to input two input signals: a state setting command and a pulse command of a different system different from the command. 2. A circuit that can perform a frequency division operation is configured including a flip-flop circuit, and a control circuit includes a transistor connected to a point where the frequency division operation of the flip-flop circuit can be turned on and off, and a transistor connected to one terminal of the bias switching circuit. 2. The integrated circuit according to claim 1, further comprising a comparator that controls on/off the transistor in response to changes in DC potential.