JPS5927911B2 - Display device control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a display device having two types of character generators, which allows switching of character generators to be easily performed by a program.

In conventional display devices, the types of characters that can be displayed on the screen are alphanumeric characters and kana characters.

If the only characters that can be displayed are alphanumeric characters or kana, it is difficult to read the displayed content, so it is desirable to be able to display sentences containing kanji on the display screen. By the way, the dot pattern for kanji is larger than the dot pattern for alphanumeric/kana, so when displaying a sentence containing kanji, you need to use a character generator for alphanumeric/kana and a character generator for kanji. It is necessary to install this on a display device and to switch between character generators as needed. Generally, the display control data and the display data displayed on the screen are prepared by a program, but when trying to switch between the alphanumeric/kana character generator and the kanji character generator as described above, It is desirable that the program can easily prepare display control data and display data, and it is also desirable that the display device has a simple structure. SUMMARY OF THE INVENTION In order to meet the above-mentioned requirements, it is an object of the present invention to provide a control method for a display device that allows a program to freely and easily switch between character generators and has a simple structure.

Therefore, the control method for the display device of the present invention includes a display code buffer, a delay buffer that delays the code data output from the display code buffer by one display clock period, and an output from the display code buffer. A code identification device that identifies whether or not the code/data to be processed is a special code, outputs an identification result signal of a predetermined value if it is a special code, and outputs an identification result signal of another predetermined value in other cases. When the output of the display code buffer and the output of the delay buffer are input to the circuit, and the identification result signal output from the code identification circuit has a predetermined value, the code identification circuit outputs the signal from the display code buffer. a multiplexer that outputs the code data that is output from the delay buffer when it has other predetermined values; and a plurality of dot matrices of characters each having a size of one unit. a first character generator that stores a dot pattern and outputs a dot pattern determined by the multiplexer and the raster row address when the identification result signal output from the code identification circuit has another predetermined value; A plurality of dot matrices of characters of various sizes are stored, and when the identification result signal output from the code identification circuit has a predetermined value, the dot matrix is determined by the code data and raster row address output from the multiplexer. a second character generator that outputs a pattern; and a second character generator that performs control to display the dot pattern output from the first character generator on the display over one display clock period, and also performs control to display the dot pattern on the display over two display clock periods. and a display control circuit that performs control to display the dot pattern output from the second character generator on the display, and timing for supplying timing signals to the display code buffer, delay buffer, and display control circuit. The invention is characterized by comprising a generating circuit. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing the relationship between character codes in the display memory area and characters on the display screen. In FIG. 1, 1 is a common bus (C-BUS), 2 is a bus interface, 3 is a timing generation circuit, 4 is a display code buffer, 5 is a delay buffer, 6 is a multiplexer, and 7
8-1 and 8-2 are character generators, 9 is a display control circuit, and 10 is a CRT unit. Although not shown, the common bus 1 includes various devices such as a processor, main memory, keyboard, etc.
A printer etc. is connected. The bus interface 2 has a function of controlling data exchange with the common bus 1 and a DMA function. Timing generation circuit 3
generates various timing clocks such as display clocks used for CRT display control. The display code buffer 4 has two one-line buffers for storing display codes, and when one buffer is outputting a display code, the display code read from the memory by DMA is written. It is becoming more and more crowded. The code identification circuit 7 identifies whether the output of the display code buffer 4 is a special code or not. In this case, the CG switching signal is output to the CGs 8-1 and 82 and the multiplexer 6. Batsuhua 5 is
This is to delay the display code from display code buffer 4 by one display clock cycle. The multiplexer 6 has the CG switching signal of the output signal of the code identification circuit 7 inputted to a select input terminal (not shown), and outputs the output signal of the display code buffer or a one-clock delay signal of the output signal (i.e., the buffer 5). output signal). Multiplexer 6 is C
When the G switching signal is on, the output of display code buffer 4 is selected. CG8-1 is a character generator for alphanumeric/kana characters, and one alphanumeric/kana character is, for example, 9X.
Represented by 7 dots. CG8-2 is a character generator for Kanji characters, and one Kanji character is represented by, for example, 9×16 dots. The display code input to CG8-1 and CG8-2 has a 1-byte configuration. The display control circuit 9 performs control to display the dot pattern read from the CG 8-1 or CG 8-2 on the CRT. FIG. 2 is a time chart showing the operation of the embodiment shown in FIG.

In Fig. 2, in synchronization with the display clock, the display codes α1, α2 special codes, Kl, α3yα47α57゜''
. It is assumed that 03 is sequentially output from the display 1-02 buffer 4. In addition, α1, α2, α3...
... represents an alphanumeric/kana code, and K1 represents a kanji code. When the display code α1 is output from the display code buffer 4, the display code α1 is output from the buffer 5 with a delay of one clock. Display code α1
is not a special code, so the output C of the code identification circuit 7
is logic [0], so the multiplexer 6 selects the output A of the buffer 5 (in this case display code α1). When the output C of the code identification circuit 7 is logic "0", CG8-1 is enabled and the display code α
A dot pattern corresponding to 1 is output from the CG8-1, and this dot pattern determined by the display code α1 and the raster row address is passed to the display control circuit 9, and then the CR
displayed on the T screen. The display code α2 is the display code.
When read from buffer 4, the embodiment of FIG. 1 operates in the same way as when display code α1 is read. When the display code is a special code, the output of the code identification circuit 7 becomes logic "1" at the falling edge of the display clock indicating the start of the next cycle. When the output C of the code identification circuit 7 becomes logic "1", the multiplexer 6 outputs the display code.
The output of buffer 4 (in this case, display code K1) is output. This display code K1 is applied to CG8-1 and CG8-2, but the output C of the code identification circuit 7 is logic "1".
In this case, CG8-2 becomes enabled and CG8
-2, a two-cycle dot pattern corresponding to the display code K1 and the raster row address is read out, and this dot pattern is passed to the display control circuit 9 and displayed on the CRT screen. In the next cycle, the display code K1 is read out from the buffer 5, the multiplexer 6 outputs the display code K1, and the display code K1 is read out from the buffer 5.
is applied to In this cycle, the output C of the code identification circuit 7 becomes logic "O" and CG8l is enabled, but the display control circuit 9 also controls CG8-2 in the cycle following the cycle in which the output C is logic "1". Continue to select dot patterns and display these dot patterns one after another on the CRT screen. As can be seen from FIG. 2, alphanumeric/kana characters are displayed over one cycle, and kanji characters are displayed over two cycles. That is, if alphanumeric characters/kana characters are displayed in one display area, kanji characters are displayed in two display areas. Figure 3A shows the relationship between the display code on the display memory and the characters on the display screen.

Figure 3A shows the relationship when alphanumeric/kana characters are displayed, and Figure 3A shows the relationship when kanji characters are displayed. As can be seen from the opening in FIG. 3, if it is desired to display a sentence containing kanji, the program only has to place the desired kanji code in the display memory area next to the special code. As is clear from the above description, the display device control method of the present invention has remarkable effects in that the program can freely and easily switch between character generators and has a simple structure. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of one embodiment of the present invention.
FIG. 3 is a time chart for explaining the operation of the illustrated embodiment, and is a diagram showing the relationship between character codes on the display memory area and characters on the display screen. 1...--1 common bus (C-BUS), 2--...-
Bus interface, 3... Timing generation circuit, 4... Display code buffer, 5-... Delay buffer, 6... Multiplexer, 7- ...Code identification circuit, 8-1 and 8-2...
...Character generator, 9--Display control circuit, 10--CRT unit.

Claims (1)

[Claims] 1. A display code buffer, a delay buffer that delays the code data output from the display code buffer by one display clock period, and whether or not the code data output from the display code buffer is a special code. a code identification circuit that identifies a special code and outputs an identification result signal of a predetermined value if it is a special code, and outputs an identification result signal of another predetermined value in other cases; When the output of the delay buffer is input and the identification result signal output from the code identification circuit has a predetermined value, the code data output from the display code buffer is output and other predetermined values are output. If it has, a multiplexer that outputs the code data output from the delay buffer, a multiplexer that stores a plurality of dot matrices of characters of one unit size, and an identification result output from the code identification circuit. a first character generator for outputting a dot pattern determined by the multiplexer and the raster row address when the signal has another predetermined value; and storing a plurality of dot matrices of two unit sized characters. and a second character generator that outputs a dot pattern determined by the code data and raster row address output from the multiplexer when the identification result signal output from the code identification circuit has a predetermined value; Control is performed to display on the display the dot pattern output from the first character generator over one display clock period, and the dot pattern output from the second character generator over two display clock periods. A display comprising a display control circuit that performs control to display a dot pattern on a display, and a timing generation circuit that supplies timing signals to the display code buffer, delay buffer, and display control circuit. Device control method.