JPH06100904B2 - Memory access device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device, and more particularly to a system including a character generator (hereinafter abbreviated as CG), a graphic image memory and a central processing unit. A memory access device used for reading character pattern data from a CG according to character code information given from an arithmetic processing unit and writing the pattern data into the graphic memory according to character display position information given from the central processing unit Is.

[Background of the Invention]

In recent years, the display system of a personal computer has been required to have high functionality, and by utilizing the limited functions of a central processing unit (microprocessor, hereinafter abbreviated as MPU) on a single chip, high-speed processing and high-definition The display is realized. In such high-performance personal computer display systems, most of them employ a character generator of 16 x 16-dot character font (abbreviated as CG below). Also,
The process of writing the character pattern data read from the CG to the graphic memory when displaying characters on the graphic screen is partially supported by hardware (bit shift, bit mask circuit, etc.), but is basically software. There is a lot to rely on. For example, in the PC-100 PC sold by NEC Corporation, its technical manual (11-1) page (11-5)
As described on the page, the MPU specifies the address to be given to the CG word by word, and once the MPU fetches the character pattern data, it writes it to the graphic memory. The hardware configuration and specific processing in this case will be described with reference to FIGS. 5 to 7.

FIG. 5 is a block diagram showing a display system circuit of a personal computer. In the figure, 1 is an MPU, 2 is a data bus, 3 is an address bus, 4 is a read / write control signal line (hereinafter referred to as R / W line), and 5 is a display control controller that outputs various timing signals for display. (Hereinafter referred to as CRTC), 6 is a display address, 7 is a display timing signal indicating that a display period is in progress, 8 is a selection circuit which is switched by the display timing signal line 7, and 9 is an RO storing character pattern data.
Character generator (hereinafter referred to as CG) that is M (Read Only Memory), 10 is an output port that latches the address information of CG9, 11 is an input port that latches the character pattern data of CG9, and 12 is the display data as a graphic image. A display memory for storing, 13 is a parallel-to-serial converter for converting the data read according to the display address 6 into visible information, 14
Is a Cathode Ray Tube (hereinafter abbreviated as CRT) that displays the contents of the display memory 12.

Next, the operation of FIG. 5 will be described. In the figure, first, CRTC
Reference numeral 5 receives operation information from the MPU 1 via the address bus 3 and the data bus 2 and starts the operation required for display. CRT14
During the display period, the display timing signal 7 is in the H'state and the selection circuit 8 selects the display address 6 as shown in the figure.
On the other hand, the display timing signal 7 is in the ^| L ^| state during the blanking period of the CRT 14, and the MPU 1 can access the display memory 12 via the address bus 3. Therefore, to newly display characters on the CRT 14, the MPU 1 updates the contents of the display memory 12 during the blanking period.

Specifically, the display memory 12 corresponding to the position where the character pattern data read from the CG9 by the MPU1 is to be displayed on the CRT14.
Write to the address of. At this time, for example, assuming that the MPU 1 can transfer data in units of words (2 bytes), 16 write operations and write address calculation are performed by software in order to display characters of 16 × 16 dots. next,
The operation when the MPU1 reads character pattern data from CG9 will be described with reference to FIGS. 6 and 7.

FIG. 6 shows how CG9 stores character pattern data. This figure shows the CG9 address space indicated by the character code information that is unique information for each character. That is, the address space indicated by the character code information of the character "A" stores the 16-word character pattern data shown in FIG. When the MPU 1 of FIG. 5 actually reads the character pattern data, the ROW address information indicating the line number is given to the CG 9 at the same time as the character code information to specify the character pattern data word by word. Specifically, the character code information "A" and
When ROW address information "4" is given to CG9, hexadecimal 1-word data "1FF8" can be read. The hardware that supports such a read operation is the output port 10 and the input port 11 in FIG. That is, MPU1 is an output port
Set the character code information and ROW address information to 10 and read the character pattern data from the input port 11. This is MP
This is to save the memory space of U1. In other words, CG
If 9 is directly placed in the memory space, 16 words per character will be required. With this method, if 2 words of input port 11 and output port 10 are placed in the memory space, all character pattern data can be read. Is possible.

Next, FIG. 7 is a flowchart of the processing relating to the reading of the character pattern data described above. As shown in the figure, in order for the MPU 1 to read one character pattern data, it is necessary to update the address information of CG9 in units of one word and output this information to the output port 10. In short, the calculation and setting of the address information given to the CG9 and the reading operation of the character pattern data are performed by the MP
U1 is doing.

As described above, in the conventional technique, when displaying one character, the MPU 1 calculates and sets the address information of the CG9 and reads the data in units of one word. Further, the address calculation of the display memory and the writing of data are performed. The time required for such software processing is about 3 ms in the case of 40 × 40 dot character data according to a certain measurement result.

[Object of the Invention] An object of the present invention is to provide a memory access device that realizes high-speed character display in a display device that displays characters on a graphic drawing, in order to eliminate such drawbacks of the prior art.

[Outline of Invention]

In order to achieve the above object, the present invention provides RO for character data.
A counter circuit that generates W address information and a circuit that holds character code information and address information of the display memory are provided, while reading arbitrary character pattern data from CG,
By writing the read character pattern data directly to a predetermined position in the display memory, high-speed character display is possible.

Example of Invention

This embodiment is designed to speed up the process of displaying characters on a graphic drawing, and controls the process of reading the character pattern data from the CG and simultaneously writing the character pattern data to the character display area of the display memory. The device is applied to a personal computer display system route.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 8 shows a system to which the memory access device according to the present invention is applied. Circuit blocks and signal lines having the same functions as those in FIG. 5 are designated by the same reference numerals as those in FIG. . In FIG. 8, 15 is a memory access device which is a main circuit block of the present invention, 16 is a CG address bus,
Reference numeral 17 is a write signal line (hereinafter referred to as a signal line) output from the memory access device 15, and 18 is a memory access device.
An enable signal line (hereinafter referred to as MAEN signal line) 15 indicating that 15 is outputting a valid signal is a plurality of address buses, 19 is a character display address bus, 23 is a character pattern data bus, 20 is a logical product circuit, Reference numerals 21 and 22 are selection circuits switched by the MAEN signal line 18. First, the operation of FIG. 8 will be described focusing on the memory access device 15. Then the first
The memory access device 15 will be described in detail with reference to FIGS.

In FIG. 8, MPU1 is an address bus 3 and a data bus 2.
The memory access device 15 is controlled via the. In this example, the MPU 1 can perform the following four controls. that is,
These are (1) identification of character code information, (2) setting of display position information, (3) start instruction of character display processing, and (4) reading of operation status of the memory access device 15. Memory access device 15, to the (3) of the start instruction receive the MAEN lines 18 and ¹ H ¹ state when, the selecting circuit as shown in FIG. 21 is the character pattern data bus 23 from the data bus 2,
The selection circuit 22 switches to the character display address bus 19. Subsequently, the memory access device 15 outputs the character code information set in (1) above and the row address information controlled internally to the CG address bus 16 together. At the same time, (2)
The address information of the display memory 12 calculated from the information set in step 1 and the row address information is output to the character display address bus 19. Furthermore, when a write signal is output to the signal line 17, the write signal is output to the display memory 12 via the AND circuit 20, so the character pattern data read according to the address information on the CG address bus 16 is displayed on the character display. Write to the address of the display memory 12 indicated by the information on the address bus 19. When the writing is completed, the internal ROW address information is automatically updated, and the character pattern data corresponding to the ROW address information is written to the address of the display memory 12. For example, in the case of a 16 × 16 dot font, data is handled in word units.
Will be done once. Finally, when the writing of the 16th character pattern data is completed, the MAEN signal line 18 becomes ¹ L ¹ state, and the selection circuit 21 is switched to the data bus 2 and the selection circuit 22 is switched to the composite address bus 24. Therefore, MPU1
By reading the state of the MAEN signal line 18, it can be determined whether or not the memory access device 15 is operating. This is the control of (4) above. In short, by applying the present invention, the character display can be performed without the MPU1 being aware of the character pattern data by only setting the character code information and the character display position information and issuing a start command of the character display processing. Of. Next, detailed operation of the memory access device 15 as one embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a memory access device as an embodiment of the present invention.
15 is a detailed block diagram of 15, in which circuit blocks and signal lines having the same functions as those in FIG. 8 are designated by the same reference numerals. In FIG. 1, 100 is an address decoder, and 101 to 10
4 is a decode signal line, 105 is a timing control circuit, 106 is an address clock line, 107 is an address clear line, 109 is a signal line indicating the write timing (hereinafter referred to as WE signal line), 110 is an oscillator, 111 is a ROW address R to generate information
OW address counter, 112 ROW address bus, 108 end signal line indicating that ROW address information for characters has been sent, 113 and 115 latch circuits for holding data, 114 character code information bus, 116 character display Vertical location bus, 1
Reference numeral 17 is a character display horizontal position information bus, 118 is an adder, 119 is a real table vertical position information bus, 120 is a NAND circuit, and 121 is a tri-state buffer circuit.

In the figure, when a display processing start command is sent via the address bus 3, a decoder signal 101 is generated in the address decoder 100. The decode signal 101 is sent to the timing control circuit 105, and the character display process is started. Here, the timing control circuit 105 sends a clear signal synchronized with the signal of the address clock line 106 to the ROW counter 111 via the address clear signal line 107, and
Initialize address information. At the same time, MAEN signal line 18 is ¹ H ¹
It becomes a state. Therefore, the NAND circuit 120 starts outputting the signal on the WE signal line 109 to the signal line 17.

On the other hand, the ROW counter 111 performs a counting operation in synchronization with the signal on the address clock line 106. Actually 16x16
When displaying dots, it is a 5-bit counter, and the lower 4 bits are the row address information and the upper 1
The bit becomes a signal to be sent to the end signal line 108. Specifically, using two TTLHD74LS163, this ROW counter 111
Can be configured. In short, ROW counter 111
Initializes the ROW address information at the start of character display, and updates the ROW address information in synchronization with the signal on the address clock line 106. In addition, the end of the character display process
It is transmitted to the timing control circuit 105 via 108. In response to this signal, the address control circuit 105 sets the MAEN signal line 18 to ¹ L ¹ again.
State.

The state of the MAEN signal line 18 can be read by the MPU 1 via the tristate bus buffer 121. That is, when the MPU 1 wants to read, specific information is output to the address bus 3 and the address decoder 100 outputs a read signal to the decode line 104. Then, the tri-state bus buffer 121 is enabled and the MAE
The state of the N signal line 18 is output to the data bus 2 and the MPU 1 reads the information.

Further, when the MPU 1 outputs specific address information, the address decoder 100 outputs a write signal to the decode signal lines 102 and 103. The latch circuit 113 sets character code information and the latch circuit 115 sets character display information by these write signals.

First, the character code information is output to the character code information bus 114 and combined with the ROW address information output from the ROW counter 111. The result is output to the CG address bus 16 as CG address information. Therefore, when the ROW address information is updated, the CG address information is automatically updated.

Next, the character display position information is displayed in the character display vertical position information bus 11
6 and the character display horizontal position information bus 117 are separately output.
Of these, the character display vertical position information is added to the ROW address information in the adder 118, and the display memory 12
Is converted to part of the actual address information of. This information is output to the actual character display vertical position information bus 119 and combined with the character display horizontal position information. The result is output to the character display address information bus as character display address information. Therefore, when the ROW address information is updated, the character display address information is automatically updated.

In short, the CG address information and the character display address information are also updated in synchronization with the signal of the address clock line 106, and the writing operation of the character pattern data corresponding to the CG address information is performed by the write signal of the signal line. Next, the series of operation timings will be described with reference to FIG.

FIG. 2 is a diagram showing a time chart of main signals of the memory access circuit 15. As shown in the figure, when the decode signal is output, the address clear signal becomes ¹ L ^{1 for} one clock width from the falling edge of the next address clock.
At this time, the row address information is initialized at the rising edge of the address clock and becomes ¹ O ¹ . MAEN at the same timing as this
The signal rises. Then, the information of the WE signal is output to the ▲ ▼ signal. On the other hand, the ROW address information is updated at the rising edge of the address clock. RO when this information is updated 16 times
The end signal, which is the upper 5th bit of the W address counter, rises. Use the rising edge of this signal to change the MAEN signal to ¹ L ¹
Indicates that the 16-word memory access, that is, the one-character display process is completed.

Next, a timing control circuit that controls such operations
105 will be described in detail with reference to FIG. 3 and FIG.

FIG. 3 is a detailed diagram of the timing control circuit 105. In the figure, in the circuit having the same function as in FIG. 1, the lock and the same signal line are denoted by the same reference numerals.

In FIG. 3, 200 2 ³ Bunshu unit, 201 is a clock line of the oscillator 110, 202 is a shift register, 203 and 204 are each Q _B and Q _D output of the shift register 202. 205 is an OR circuit, 206 is an inverting circuit, 207 to 210 are edge trigger type flip-flop circuits (hereinafter referred to as FF), 211 is a negative logic output signal line of FF208, 212 is a positive logic output signal line of FF209. , 213 are NAND circuits, and 214 is an OR circuit.

The frequency divider 200 in the figure sends a signal obtained by dividing the clock of the oscillator by 2 ³ to the shift register 202. Shift register 2
02 generates signals having various phases by synchronizing this signal with the clock of the oscillator clock line 201. Against specific Q _A signal, i.e. the address clock signal one clock delayed signal Q _B signals, 3-clock delay signal is a Q _D signal. Such a frequency divider 200 and shift register 202 are respectively
It can be easily realized with TTL HD74LS393 and HD74LS164.
OR circuit 205 outputs a WE signal as inputs the Q _B signal line 203 and the Q _D signal line 204. The series of timings are shown in the upper half of FIG.

FF207 to FF210 in Fig. 3 have the same function, and TTLHD74L
It operates exactly the same as S74. Therefore, when the decode signal enters the decode signal line 101, the Q output of FF207 becomes ¹ L.
Become ¹ . Further, the Q output signal of FF207 is latched at the rising edge of the signal obtained by inverting the address clock by the inverting circuit 206 in FF208. Furthermore, the Q output signal of FF208 is FF2.
In 09, it is caught at the rising edge of the same clock as FF208. Here, the NAND circuit 213 is connected to the output signal line 211 and F of the FF208.
The Q output signal line 212 of F209 is input and an address clear signal is output.

Further, in the OR circuit 214, the address clock line 106 is ¹ H ¹
And the address clear line 107 is in the ¹ L ¹ state, PR of FF210
Send a signal to the terminal. This signal causes the MAEN signal line 18 which is the Q output of the FF 210 to be in the ¹ H ¹ state. Finally, at the rising edge of the signal on the end signal line 108, the MAEN signal line 18 which is the Q output of the FF 210 enters the ¹ L ¹ state. The timing of these series is the fourth
Shown in the lower half of the figure. The detailed configuration and timing of the timing control circuit 105 have been described above.

Although the memory access device 15 has been described as the embodiment of the present invention, the present invention is not limited to this example. For example, considering the correspondence to the character display processing of 32 × 32 dots, in FIG. 1, the bit number of the ROW counter 111 is set to 7 bits, and the addition operation of the lower 5 bits information and the character display vertical position information is performed. Not only this, it is necessary to perform the addition operation of the second highest-order 1-bit information of the ROW counter 111 and the character display horizontal position information. Therefore, the configuration is such that an adder is added.

Further, the present embodiment can be applied to the control circuit in a printing apparatus such as a laser beam printer provided with a CG and a graphic image memory with the same hardware configuration as the present embodiment.

Finally, when the present invention is applied to a personal computer display system circuit,
Conventionally, the MPU performed reading and writing of character pattern data word by word, whereas the present invention uses MP.
U only sets the character code information and character display position information, and the processing is done by hardware, so the load on the MPU is reduced. At the same time, by reading and writing character pattern data at the same time, either CGROM or graphic memory can be used. The time represented by the product of the longer cycle time and the number of words of 1-character data becomes the processing time for 1-character display, and high speed can be realized. Specifically, with a cycle time of 500 nsec, the character display processing time of 40 x 40 dots is
50 microseconds.

[Effects of the Invention] As described above, according to the present invention, the processing speed t _pro depends on the longer cycle time t _cyc of the CG or the display memory when performing the one-character display processing. If the character data width is M bytes and the data width to be processed is N bytes, Next, high-speed processing is realized. Specifically, the MPU (8086) took about 2 ms to display characters of 40 x 40 dots, but when the present invention is applied, the cycle time is set to 500 nsec and 50 µsec for word processing and byte processing. The processing time is 100 μs. Furthermore, while the conventional MPU processed character pattern data 1 byte or 1 word at a time,
Since it is possible to perform the one-character display processing only by setting the character code information and the character display address information, there is an effect that the load of the MPU is lightened and the MPU can perform other processing at the same time as the character display processing.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a block diagram showing details of a timing control circuit in FIG. 1, and FIG.
FIG. 5 is a time chart, FIG. 5 is a block diagram showing a conventional example of a personal computer display system circuit, FIG. 6 is an explanatory view showing a state in which character pattern data is stored, and FIG. 7 is a flow chart for reading out one character data. , FIG. 8 is a block diagram showing a system to which the present invention is applied. 1 ... MPU, 5 ... CRTC, 9 ... CG, 12 ... Display memory, 15 ... Memory access device, 105 ... Timing control circuit, 111 ... RO
W address counter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Suzuki, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Nikkei Video Engineering Co., Ltd. (72) Takashi Maruyama 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory (56) References JP-A-61-83585 (JP, A)

Claims (1)

[Claims] 1. A character processing unit receives character code information and character display position information from a predetermined processing device, reads character pattern data from a character generator according to the character code information, and generates the character pattern data according to the character display position information. A first selecting means for selecting one of two addresses of the output address of the processing device and the write address as an address to the display memory in the display memory according to the write address. A memory access device for writing via one of the output data and the character pattern data read from the character generator as a write data to be written to the display memory. The character code information and characters given from the processing device Holding means for holding position information, means for sequentially generating ROW address information, read character pattern data of the character generator from the generated ROW address information and character code information held in the holding means Timing for generating a read address to be written, a means for generating a write address for writing the character pattern data in the display memory from the generated ROW address and the character position information held in the holding means, and timing. A timing circuit for selecting the write address of the first selecting means, and a timing for selecting character pattern data read from the character generator of the second selecting means. And the timing of the write operation of the display memory The memory access device is controlled such that the character pattern data read from the character generator at the read address is directly written to the display memory at the write address.