JPS5927919B2 - Electronic musical instrument keyboard circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention divides a keyboard switch into a plurality of blocks, converts the on/off digital signals of the keyboard switch into DA for each block, and converts the on/off digital signals of the keyboard switch into analog output signals that are time-division multiplexed between the blocks through a small amount of wiring. The present invention relates to a keyboard circuit for an electronic musical instrument that detects an event key signal by converting it back into a digital signal by AD converting the signal after transferring the event key signal.

Conventionally, as a method for detecting the on/off state of a keyboard switch in a keyboard circuit, the first method is to sequentially scan all the keyboard switches and time-division multiplex the on/off state with a signal of '1-'00'. was proposed, but it had the drawback that it required a long scanning time when there were a large number of key switches, and the response time from key operation to sound production was slow.

In order to compensate for this drawback, it is conceivable to increase the scanning speed of the key, but this increases the operating speed of the circuit, which may lead to a decrease in the reliability of the circuit. In order to improve this, a second method was proposed. The second method is to divide the key switches into multiple blocks, check in each block whether there is a key switch in the on state, scan between the blocks to detect the event block, and detect the event block. The block is scanned again to search for keys in the key-on state. However, since this second method has two scanning modes: scanning between blocks and scanning within each block, the keyboard switch peripheral circuit and key code generation circuit are complicated. Furthermore, since the keyboard switch peripheral circuit and the key code generation circuit are usually provided separately, there is a problem in that the number of wires between them is large and the number of man-hours required for connection is extremely high. SUMMARY OF THE INVENTION An object of the present invention is to provide a keyboard circuit for an electronic musical instrument that reduces wiring from a keyboard switch peripheral circuit to a key code generation circuit and simplifies the circuit for scanning and detecting event keys in the key code generation circuit. In order to achieve the above object, the keyboard circuit of the electronic musical instrument of the present invention includes a plurality of DA converters that scan each block of a group of keyboard switches divided into a plurality of blocks and input on/off signals for the keyboard switches; a multiplexer that sequentially selects analog output signals of the DA converter;
The present invention is characterized by comprising an AD converter that returns the output analog signal of the multiplexer to an on/off signal of a keyboard switch, and further includes a circuit for detecting an event key whose on/off state has changed from the output of the AD converter, and is inputted in parallel. The present invention is characterized by comprising an encoder that prioritizes event key signals and outputs a key code corresponding to the highest priority event key, and means for temporarily stopping scanning within the program while outputting the event key code. It is something.

Hereinafter, the present invention will be explained in detail with reference to examples.

The present invention is composed of a keyboard peripheral circuit and a key code generation circuit.

FIG. 1 is an explanatory diagram of an embodiment of a keyboard peripheral circuit according to the present invention.

In the figure, the keyboard switch 11 is divided into m blocks of n blocks, and an n-bit input DA is connected to each block.
m converter groups 12 are provided. Only one output of each DA converter is selected by the analog multiplexer 13. A counter 44 in the key code generation circuit, which will be described later, counts the clock φ2 and sets the block code to 0 via the output signal line 15.
, 1, 2, . . . , m and is applied to the multiplexer 13. The multiplexer 13 inputs the input from the DA converter 12 to DAC1, DAC2, .
One analog signal 14 of the analog signals in the order of DACm
Since the output is output through the , a large number of conventional output wirings can be omitted. FIG. 2 shows a specific circuit of the keyboard switch and DA converter shown in FIG. 1.

The output of the keyboard switch 20 is at the level "'F'" when it is on, and at the level "O" when it is off.The keyboard switches 201 to 20
The output of n is parallel-series R-2R via the buffer circuit 21.
The signal is DA-converted by the resistor network 22, and further sent to the multiplexer 13 via the buffer circuit 23, where it is time-division multiplexed. It goes without saying that the DA converter made up of the buffer circuits 21 and 23 and the resistor network 22 can be constructed from an integrated circuit (IC). FIG. 3 is an explanatory diagram of an embodiment of the key code generation circuit of the present invention.

In the figure, an analog signal from a multiplexer 13 is applied to an AD converter 31, and is returned to a "1-"0" signal corresponding to the on/off state of the key switch. The output of the AD converter 31 is expressed in parallel as the on/off state of the key switch for each block is represented by "1-"O". The output of the AD converter 31 is latched by the first latch circuit (4) 32 by the clock φ2. Since the AD converter 31 requires time for conversion, it was decided to latch the output of the AD converter 31 in the first latch circuit (1) 32, and perform the AD conversion within one clock of clock φ2. The output of the first latch circuit ( ) 32 is the shift register 3
3, a second latch circuit (l) 34, and an exclusive 0R gate group (EXOR) 35. The shift register 33 has an n-bit input and is composed of m stages, and is shifted by the clock φ2. Therefore, the shift register 33
The output is an on/off signal of the key switch of the same block one cycle of block scanning in the keyboard peripheral circuit with respect to the input, and is delayed by one cycle of block scanning. The second latch circuit (]]) 34 is a clock φ2
latches the output of the first latch circuit (1) 32.

Since the EX-0R gate group 35 inputs the input and output of the shift register 33 and compares the on/off data that differs by one cycle during block scanning, the output is "1" for the event key that changes on/off of the key switch. An event key signal is taken out, and this event key signal is clocked by the clock φ
2 is written to flip-flop group 36. The output of the flip-flop group 36 is input to the 0R gate 37,
0R gate 37 is “1” when any of the human power is “1”.
1” event signal is output.The event signal is A
The ND gate 38 is closed, the passage of the clock φ1 from the clock generator 45 is stopped, and the pulse output of the clock φ2 is temporarily stopped. Also, the event signal is AND gate 39
Open, pass clock φ1, and AND clock φ3.
It is given to the gate group 40. Further, the output of the 0R gate 37 is output as a sign bit signal. On the other hand, the output of flip-flop group 36 is sent to priority encoder 41.

The priority encoder 41 assigns priorities to the inputs,
Outputs the binary code assigned to the highest priority bit among the bits inputting "1" as a key code. As this encoder 41, for example, an encoder model number "SN74l47" manufactured by Texas Instruments is applied. The output key code of this priority encoder 41 is given to a multiplexer 42, and the second latch circuit (W3
The signal line corresponding to the flip-flop that outputs the 1" signal corresponding to the key code is selected from among the outputs of 4 and output. Therefore, if the event key is on, "゜1" is output.
If the key is off, "0" is output from the multiplexer 42 as an on/off bit. This means that when the key is on, the output of the first latch circuit (4) 32 is "1" and the output of the shift register 33 is "0", and when the key is off, the output of the first latch circuit (4) 32 is "1". This is because the output of the shift register 33 becomes "0" and the output of the shift register 33 becomes "1". The output of the multiplexer 42 is output as an on/off bit signal. The output key code of the priority encoder 41 is given to an AND gate group 40, and when the AND gate 40 is opened by the clock φ3, the decoder 43 inputs the key code, and the key code is selected by the corresponding flip-flop 36, that is, the priority encoder 41. Resets the flip-flop 36 of the input ゜61゛. The output of the priority encoder 41 is then output as a key code. Further, the counter 44 is a counter that counts using the clock φ2.
The output of 4 is output as a proc code. As described above, the sign bit indicating the existence of an output code, the on/off bit indicating whether the event key is on or off, the program code to which the event key belongs, and the key code are output simultaneously.

FIG. 4 shows an example of a time chart when three event keys occur in the second block.

In the figure, when an event signal is generated, the AND gate 38 is closed and block scanning is stopped, but when three time slots are completed, the event signal disappears again and block scanning is started.

That is, as explained in FIG. 3, the clock φ in FIG.
1, the count value (block code) of the counter 37 shown in FIG. As a result, one code is stored in the first latch circuit 32 shown in FIG. Stopping is performed at intervals equal to the number of event keys. This priority order is determined by resetting and controlling the flip-flop 36 via the decoder 43 by the clock φ3 shown in FIG. In this way, when there is no change in the on/off state of the key switch, all the key switches are scanned by clocks equal to the number of blocks, and when there is a change in the on/off state of the key switch, the scanning clocks are stopped by the number of times that have changed, and the clocks corresponding to the event key are scanned. Information is output in its original priority order.

In this way, the configuration is simplified because the event key is detected in one scan mode rather than in two scanning modes as in the conventional proposal. As explained above, according to the present invention, in the keyboard peripheral circuit, the keyboard switch is divided into a plurality of blocks, the on/off digital signal of the keyboard switch is DA-converted for each block, and the keyboard switch is time-divided between the blocks. The signal is transferred as a multiplexed analog output signal to the key code generation circuit and then AD converted.

As a result, the keyboard peripheral circuit and the key code generation circuit are connected only by the signal lines for the block code and analog signal for key information, thereby reducing the amount of wiring and helping to reduce the cost of man-hours. In addition, the key code generation circuit detects an event key with a circuit consisting of a shift register and a group of exclusive 0R gates, outputs it in priority order using a priority encoder,
By using means for temporarily stopping the scanning of the keyboard block while outputting the event key code, the event key can be detected in one scan, which is useful for simplifying the configuration of the key code generation circuit. It is something.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the keyboard peripheral circuit of the present invention, FIG. 2 is a specific circuit example of the main part of FIG. 1, FIG. 3 is an explanatory diagram of an embodiment of the key code generation circuit of the present invention, and FIG. The figure is a time chart explaining the operation of the embodiment shown in FIG. 3. In the figure, 11 is a keyboard switch, 12 is a DA converter, 13 is an analog multiplexer, 14 is an analog signal line, and 15 is a block code signal line. , 31 is an AD converter, 32 is a patch circuit (4
), 33 is a shift register, 34 is a latch circuit (with),
35 is an exclusive 0R gate group, 36 is a flip-flop group, 37 is an 0R gate, 38, 39, 40 are AND gates, 41 is a priority encoder, 42 is a multiplexer, 43
44 is a counter, and 45 is a clock generator.

Claims (1)

[Claims] 1. A plurality of DA converters that scan each block of a keyboard switch group divided into a plurality of blocks and input on/off signals of the keyboard switches, and analog output signals of the plurality of DA converters. 1. A keyboard circuit for an electronic musical instrument, comprising a multiplexer for sequential selection, and an AD converter for returning an analog signal output from the multiplexer to an on/off signal for a keyboard switch. 2. A plurality of DA converters that scan each block of a keyboard switch group divided into a plurality of blocks and input on/off signals of the keyboard switches, and a multiplexer that sequentially selects analog output signals of the plurality of DA converters; It includes an AD converter that returns the output analog signal of the multiplexer to an on/off signal of the keyboard switch, and further includes a circuit that detects an event key that has changed its on/off state from the output of the AD converter, and has priority over the event key signal that is input in parallel. A keyboard circuit for an electronic musical instrument, comprising: an encoder that outputs a code corresponding to a highest priority event key; and means for temporarily stopping scanning within the block while outputting the event key code. 3. The circuit for detecting the event key comprises a shift register that outputs the digital signals inputted in parallel with a delay of one cycle of intra-block scanning, and means for detecting different levels of the digital signals corresponding to the shift register. A keyboard circuit for an electronic musical instrument according to claim 2, characterized in that: