JPS5929034B2 - Multi-frequency signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency signal generator for a digital exchange.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-frequency signal generating device that generates a make-broken multi-frequency signal composed of digital signals, which has not been known in the past.

To achieve the above object, a multi-frequency signal generating device according to the present invention is comprised of a storage device that stores multi-frequency signal data, a memory timer that sets a certain time, and a register that stores read data from the storage device. .

Then, the multi-frequency signal data stored in the storage device is read out using the order signal, and at the same time, a set signal that excites the memory timer and sets the register used as a buffer in the storage device while the timer function is working. and stores the read data of the storage device in the register. Also, when the timer function stops, a register reset signal is issued to clear the register. In this way, by creating register set signals and reset signals using the timer, it is possible to generate multi-frequency signals in make and break states. First, the operating principle that is the basis of the present invention will be explained.

The basic operation is to store the value of PCM data obtained by sampling a 2-frequency mixed wave every 125 μs into a storage device.
This is possible by reading it out in the evening. The data of the multi-frequency signal converted into PCM is stored in the memory area of the storage device. If the storage capacity for one type of multi-frequency signal is nXW bits (bit length x word length), the total multi-frequency signal will be 15 as shown in Section 1 at the end of the detailed description of the invention.
Since different types are required, the total storage capacity of the storage device is 15 x nX
W bit is required.

This storage device can be easily realized using programmable read-only memory, which has recently shown rapid development. Multifrequency signals are assigned to this storage device as shown in FIG. 1A. As for the data of the multi-frequency signal, data obtained by sampling a waveform obtained by mixing two frequencies into S pieces as shown in FIG. 3C is stored in the word direction of the storage device as shown in FIG. Here, the number of samplings S corresponds to the number of words W of one frequency of the storage device. Multi-frequency signals can be generated by reading sampling data from the storage device every 125 μs. This is shown in Figure 2.
An example will be explained in which 5 μsec is used for N multiplexing. (700+900)H in the first multiplex time slot of N multiplexes
When trying to obtain a PCM signal of the mixed wave of z (MFl in Table 1), the M of the storage device is
This is possible by reading the address where Fl is stored. If you read this as W word (time is 1
PCM data of a mixed wave of 25×WμSec)(700+900) Hz is obtained for one period, and by repeating this, a continuous PCM signal is obtained. Next, the present invention will be further explained with reference to the drawings.

The structure of the present invention can be represented by the block diagram shown in FIG. The orders include the following signals. One is an address signal that indicates how many times out of N multiplexing the multifrequency signal is to be generated, and the other is a data signal that indicates what kind of multifrequency signal is to be generated in the addressed channel. .

When an order enters the memory control unit 1, an address signal and a data signal are stored.The address signal indicates the number of multiplexes, and the data signal specifies and reads out the address of the storage device 2. On the other hand, at the same time that the address signal and data signal are stored, a flag indicating that the signal has been detected is set in the memory control section 1, and the memory timer 4 is excited. The memory timer 4 is counted by frame pulses generated cyclically, and when it has counted up for a predetermined period of time, it outputs a clear signal to the memory timer 7 to clear the flag in the memory control section 1. By doing so, the memory timer 4 operates as a timer. The flag output 8 of the memory control unit 1 and the clock are AND'ed to obtain the set signal 5 of the register 3, and the inverted signal of the output 8 and the clock are AND'ed to form the register 3 set signal 6. The make-break operation is performed as follows.

First, when an order signal enters the memory control unit 1, output data is output to the storage device 2 by an address signal and a data signal. At the same time, a signal 1'' is applied to the flag output 8 of the memory control unit 1, and a set signal of the register 3 is issued to set the output data of the storage device 2.On the other hand, while the memory timer 4 is operating as a timer, Since the state of the flag output 8 does not change, the read data of the storage device 2 continues to be output from the register and enters the make state.Here, when the memory timer 4 stops after a predetermined period of time has elapsed (for example, 50 msec). , a clear signal for clearing the flag of the memory control unit 1 is generated at 7, the state of the flag output 8 is set to 0'', and a reset signal 6 is obtained. The output of the register 3 is reset by the reset signal 6, resulting in a break state and no-signal data is obtained.

Next, when the second order signal is input, the memory timer 4 starts operating again and enters the make state, and after a predetermined time elapses, the memory timer 4 enters the break state. By repeating this process, a make-break multi-frequency signal is generated. When the order signal comes every 100 msec as shown in FIG. 4A, a make-break multi-frequency signal as shown in FIG. 4B is generated at the output of the register 3.

Here, the memory timer 4 is composed of an add-on counter 9 and a memory 10 as shown in FIG.

The add-on counter 9 has a function of adding +1 to the input data value when a pulse is applied to UP. The output of the and-on counter 9 is connected to the input of the memory 10, and the output of the memory 10 is connected to the input of the add-on counter 9. For example 5
If you want to obtain a 0mse9 timer, take the frame pulse that appears every 1mse, the flag output 8, and an AND circuit, and when the flag output 8 comes out, it is added to the 1mse period. The added data is stored in the memory 10, the stored data is entered into the add-on counter 10, and +1 is added again after 1 msec. By repeating this, when the output of the add-on counter 9 reaches 50, a signal is generated at 7 to clear the flags of the add-on counter 9 and the memory control section 1 shown in FIG. 3, and the state of the flag output 8 is changed. U
Prevent pulses from appearing on P. In other words, the timer is stopped. The memory timer 4 operates as described above. With the above configuration, when an order signal is received, the memory timer is activated and a set signal is issued.
A make state can be created by setting the multifrequency signal data in the storage device 2 in a register, and a break state can be created by issuing a set signal when the timer stops and clearing the register.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the memory allocation in the storage device shown to explain the basic operating principle of the present invention, and FIG. 2 is a diagram showing the memory allocation in the storage device shown to explain the basic operation of the invention. FIG. 3 is a block diagram showing an embodiment of the multi-frequency signal generator according to the present invention, FIG. 4 is a diagram for explaining the make state and break state, and FIG. 5 is a diagram showing the memory read procedure. It is a figure showing an example. 1...Memory control section, 2...
Storage device, 3...Register, 4...Memory timer, 5...Set signal, 6...
・Reset signal, 7...Clear signal, 8...
... Flag output, 9 ... Add-on counter, 10 ... Memory.

Claims (1)

[Claims] 1 Multi-frequency signal generation that includes a storage device that stores multi-frequency signal data, a memory timer that can set a certain time, and a register that stores read data from the storage device, and generates a multi-frequency signal based on an order signal for reading out the storage device. The device reads the multi-frequency signal data of the storage device using the order signal, and at the same time excites the timer and outputs a register set signal while the timer continues, the data of the storage device is stored in the register, and the timer is activated. A multi-frequency signal generating device characterized in that when a register is disconnected, a register reset signal is issued, and the register is cleared to generate no-signal data, thereby generating a make-broken multi-frequency signal.