JPS5929139B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which another object is bonded to a silicon semiconductor element having an n-type surface using aluminum as a brazing material. It is.

In semiconductor devices, a metal support made of tungsten or molybdenum is bonded to one or both sides of a silicon element in order to improve the mechanical properties of the silicon element. This support plays the role of an electrode on the one hand (hereinafter this metal support will be referred to as support electrode). Conventionally,
Aluminum has been used as a brazing material to bond the support electrode and the silicon element.

However, during this bonding, the silicon dissolved in aluminum precipitates again on the n-type silicon surface to form a regrowth layer, and as a result, the n-type is reversed to the p-type, and as a result, when used as a semiconductor device, the forward direction It has the disadvantage of causing a voltage drop. In order to improve the above drawbacks, conventional methods have been to reduce the thickness of the aluminum layer, or to rapidly cool the joint during bonding, which causes a large amount of pentavalent elements such as phosphorus and arsenic to diffuse into the n-type surface layer. Several methods have been tried, but no sufficient effect has been achieved.

An object of the present invention is to eliminate the drawbacks of the prior art described above and to manufacture a semiconductor device in which the forward voltage drop of a semiconductor device in which another object is bonded to a silicon element using aluminum as a brazing material can be reduced as much as possible. The purpose is to provide a method. In order to achieve the above object, the present inventors have conducted various studies on the relationship between the surface shape of the surface to be bonded and the silicon regrowth layer. We found that when a groove-shaped recess (hereinafter defined as a crevasse) is formed and bonded to a support electrode using aluminum as a brazing material, a stable semiconductor device with a small forward voltage drop can be obtained. .

That is, the present inventors created a 200 μ square frame by alkaline photoetching of an n+ type silicon element,
After evaporating aluminum to a thickness of 5 μm, the melting behavior of aluminum and n+ silicon was observed using a high-temperature microscope. Furthermore, the correspondence between the surface morphology of n+ silicon (especially crevasses) and the growth location of the regrowth layer was investigated using a scanning electron microscope. As a result, it was found that aluminum was preferentially dissolved in crevasses with higher phosphorus concentrations, and that regrowth layers were less likely to grow in crevasses, as shown in later examples. In this way, since the regrowth layer is difficult to form in the crevasse, many discontinuous portions of the regrowth layer can be formed on the bonded surface of the silicon element, and as a result, the formation of a P-type inversion layer 5 is prevented. It has become clear that the forward voltage drop is significantly reduced. The present invention has been made based on the above findings, and provides a method for bonding the surface of a silicon semiconductor element having an n-type surface to another object using aluminum as a brazing material. It is characterized in that the surface is etched in advance with an alkaline aqueous solution, then a pentavalent element is diffused onto the etched surface, and then brazed. It is characterized by being brazed.

In the present invention, the surface of the silicon element to be adhered is of n type, but this also includes n+ type.

Therefore, the silicon semiconductor element itself may be a silicon semiconductor having an n-type surface.

The surface of the silicon semiconductor element having the n-type surface is first etched with an alkaline aqueous solution, and the alkaline aqueous solution is preferably an aqueous solution of, for example, about 10% by volume of sodium hydroxide or potassium hydroxide. is used.

The alkaline aqueous solution may contain an etching inhibitor and the like. Examples of such etching agents include Chemsolve (produced by Mallinckrodt Chemical Works).
Product name). Etching can be carried out by immersing the surface of the silicon element to be treated in the above alkaline aqueous solution for a predetermined period of time, but the etching temperature is usually 30 to 60°C. The duration is 30 minutes to 2 hours. Due to the etching process described above, many crevasses are formed on the surface of the silicon element to be adhered. A pentavalent element is then diffused into the etched n-type layer of the silicon element.

The pentavalent element is preferably phosphorus, but other elements such as arsenic may also be used. This diffusion may be carried out under normal conditions used in the manufacture of semiconductor devices; for example, the semiconductor element may be exposed to a phosphorous vapor phase at a temperature of about 1000 DEG C. The phosphorus diffusion concentration of the surface of the n-type silicon to be adhered is usually 1×1020 at0 ms/Cc or more, preferably 1×1020 to 2×1021 at0 ms/Cc. In the present invention, more preferable results can be obtained by performing etching again with an aqueous alkali solution after the phosphorus diffusion. This alkaline etching may be performed in the same manner as described above. Hereinafter, the present invention will be explained in more detail with reference to Examples.

Example + The following two treatments were performed on the brazing surface of an n-type silicon element, and the n+-type surface was observed using a scanning microscope.

(1) An n+ type silicon element is immersed in an aqueous solution containing 10% NaOH as a main component at 40° C. for 1.5 hours, air-chilled, and then subjected to phosphorus diffusion at various concentrations.

(2) After performing the phosphorus diffusion in (1), further (1)
Perform the same etching process as above.

(3) Performing only phosphorus diffusion at various concentrations (comparative example)
.

n+ obtained by the methods (1) and (3) above
An example of a scanning electron micrograph (microscope magnification: 500 times) of the surface of a silicon element is shown in FIG.

That is, in the figure, A is the n+ type silicon element surface (phosphorus diffusion concentration 5 x 1020a) obtained by the method (1) above.
t0ms/Cc), B is the n+ type silicon element surface obtained by the method (1) above (phosphorous diffusion concentration 1×102
0 at0 ms/Cc) and C are diagrams respectively showing the n+ type silicon element surface (phosphorus diffusion concentration 1×1020 at0 ms/Cc) obtained by the method (3) (conventional method). Note that the phosphorus diffusion concentration on the surface of the n+ type silicon element was determined using an X-ray microanalyzer using a sample subjected to activation analysis as a standard. As is clear from the figure, the surface of the n+ type silicon element formed by method (3) (conventional method) consists of hemispherical protrusions, whereas
) It can be seen that the silicon element surface obtained by the method consists of many crevasses.

In addition, in the treatment of the present invention, when the phosphorus diffusion concentration is low, A
It can be seen that the depth of the crevasse and the proportion to the total area are larger in case B (5×1020 at0 ms/Cc) than in case B (1×1021 atnms/Cc) where the phosphorus diffusion concentration is high. Next, the n+ type silicon element treated by the methods (1) and (3) above was bonded to a supporting electrode made of molybdenum using aluminum as a brazing material, and the cross section of the bonded part of the diode was assembled using a conventional method. Photographs (microscope magnification: 400x) are shown in Figures 2A and B.

In the figure, the first layer 1 from the top is a molybdenum supporting electrode layer;
The second layer 2 is a MOSi2 layer, the third layer 3 is an Al-Si alloy layer, the fourth layer 4 is a regrowth layer, and the fifth layer 5 is an n+ type silicon layer. As is clear from the figure, in the case A according to the present invention
In case B, the regrown layer 4 of silicon is well interrupted, but in case B using the conventional method, there is no interruption in the regrown layer, and the n+ type silicon layer is completely covered with the regrown layer. I know that there is.

In addition, the methods (1) and (3) above (phosphorus diffusion concentration 5
An example of the frequency distribution of the forward voltage drop value at a current of 15 A for a diode manufactured by the method (X1020at0ms/Cc) is shown in A and B in FIG. 3, respectively.

It is clear that case A of the present invention has a smaller forward voltage drop than conventional method B. Further, FIG. 4 shows forward voltage drop values (current 15 A) of a similar diode when the phosphorus diffusion concentration of the n+ silicon layer is varied.

In the figure, 6 shows the case according to the method (3) (conventional method), 7 shows the case according to the method (1) (the present invention), and 8 shows the case according to the method (2) (the present invention). It is clear that the forward voltage drop value is much smaller in the cases (7 and 8) of the present invention than in the case of the conventional product 6, and a stable value can be obtained. In addition, in the case of conventional products, 6 is highly dependent on phosphorus concentration, and for example, in order to obtain a voltage drop value of 1.6 or less, the phosphorus diffusion conditions are limited to a concentration of 4 to 7 x 1020at0ms/Cc. However, according to the present invention, in order to obtain the same 1.6V, the concentration must be 1020at0m
Just make it s/Cc or more. In other words, the phosphorus concentration of the n+ silicon layer can be varied, making it suitable for all kinds of applications. For example, in large diameter diodes, warping occurs due to high concentration phosphorus diffusion, but this can also be prevented by reducing the phosphorus concentration to 5×1020 at0 ms/Cc or less. In addition, in the present invention, the reason why the silicon regrowth layer is broken due to phosphorus diffusion after forming a crevasse in a silicon element is that a large amount of phosphorus diffuses in the crevasse area, and phosphorus segregation occurs here. The crevasse where phosphorus becomes more easily segregated has a lower melting point and melts into the aluminum the fastest, and the crevasse with a high phosphorus concentration still has a low melting point.
It is assumed that this is because the regrowth layer grows in many places other than the crevasse.

As described above, according to the present invention, the forward voltage drop value of a semiconductor device in which another object is bonded to a silicon element using aluminum as a brazing material can be reduced, and the dependence on phosphorus concentration can be reduced.
A stable voltage drop value can be obtained.

[Brief explanation of the drawing]

FIGS. 1A, B, and C are diagrams showing examples of scanning electron micrographs of the surface of an n+ type silicon device obtained by the present invention and the conventional method, respectively. FIG. 3 is a characteristic diagram showing an example of the frequency distribution of forward voltage drop values, and FIG. 1 is a characteristic diagram showing changes in forward voltage drop values of diodes manufactured according to the present invention by changing the phosphorus diffusion concentration. Explanation of symbols, 1...Supporting electrode layer, 3...
・Al-Si alloy layer, 4...Regrowth layer, 5...
...N+ type silicon layer.

Claims (1)

[Scope of Claims] 1. In a method for manufacturing a semiconductor device in which the surface of a silicon semiconductor element having an n-type surface is bonded to another object using aluminum as a brazing material, the surface of the n-type surface to be bonded is preliminarily soaked in an alkaline aqueous solution. 1. A method of manufacturing a semiconductor device, comprising etching the etched surface, diffusing a pentavalent element onto the etched surface, and then brazing. 2. A method for manufacturing a semiconductor device according to claim 1, wherein the pentavalent element is phosphorus. 3. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the alkali is sodium hydroxide or potassium hydroxide. 4. In a method for manufacturing a semiconductor device in which a bonded surface of a silicon semiconductor element having an n-type surface is bonded to another object using aluminum as a brazing material, the bonded surface of the n-type surface is etched in advance with an alkaline aqueous solution, and then A method for manufacturing a semiconductor device, which comprises diffusing a pentavalent element onto an etched surface, further etching with an alkaline aqueous solution, and then brazing. 5. A method for manufacturing a semiconductor device according to claim 4, wherein the pentavalent element is phosphorus. 6. A method for manufacturing a semiconductor device according to claim 4 or 5, wherein the alkali is sodium hydroxide or potassium hydroxide.