JPS592990B2 - magnetic bubble memory chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a magnetic bubble memory chip, and more particularly, to an improvement in a magnetic bubble memory chip, which is connected by a plurality of connected gates each having a mode of operation determined by a magnetic field generated by a current flowing through a gate control conductor. In a magnetic bubble memory chip having multiple magnetic bubble transfer paths, the logical configuration can be changed by creating a physical configuration that allows changing the connection method between multiple gate control conductors.

This invention relates to a so-called adaptive structure type magnetic bubble memory chip. Although there are magnetic bubble memory chips based on various drive principles, most of them have advantages such as high speed, non-volatility, and high reliability, and are considered promising as high-speed auxiliary memory, file memory, etc.

However, due to the lack of flexibility in the structure and configuration of the chip,
When realizing a memory device by combining a large number of these, (1) create separate dedicated chips for each purpose, or (i (In order to avoid increasing the operating time or complicating the control), there is no choice but to use it for various purposes.In the case of the former (i), the product is manufactured in one process. Since the number of chips to be used is reduced, a drawback arises in that the extent of cost reduction due to mass production effects is reduced15.

On the other hand, in the case of the latter (ii), even if the chip configuration is optimal for a certain application, it may not necessarily be optimal for other applications, so it will not be able to demonstrate its original performance. A defect occurs. These defects also apply to the dual-layer conductive film current-driven multi-segmented chip that the applicant has separately disclosed, which is considered to be relatively versatile, so we will not provide an explanation of this chip. to make the existing flaws clearer. A typical configuration of this multi-segmented chip is as shown in Fig. 1, F5, on a substrate film 1 that carries magnetic bubbles, and in order to define the transfer path of the magnetic bubbles in the substrate film, Two-layer conductor films 2 and 3 each having a hole pattern are meandered in a direction perpendicular to the transfer path.

'0 That is, at the same position of the two-layer conductor films 2 and 3, slots 4 with a part of the right end left for energization and slots 5 with a part of the left end left for energization are alternately provided to form a plurality of rows. It is divided into regions (in the figure, only six lines are shown for the minor loop region, but normally there are as many as 5 rows), and a predetermined timing is provided at both ends of each conductor film 2, 3. The related driving voltages V, , V2 are applied to drive the bubbles in the substrate film 1 by the magnetic field generated by the current.

Incidentally, the magnetic bubbles and the perforation patterns of each conductive film are not shown in FIG. These will be shown later in the explanation of an example of the structure of the inter-row connecting gate. In a chip with such a physical configuration, its logical configuration (configuration focused on chip functions) is typically as shown in the second diagram.

In other words, if the two-layer conductor films 2 and 3 are divided into h+2 rows, each row region of h rows, excluding the upper and lower row regions, is provided with a group of n columns of small loops formed into loops with an opening pattern. 1 (1-1, 2, . . . , n) that are vertically adjacent to each other, the slot 4 shown in the first diagram
, 5 are connected by a swap gate (schematically indicated by a round trip line 6), respectively, to form n columns of minor loops Mi (1=1, 2, . . .
..., n), and the top and bottom of each minor loop are the bottom row major loop M1 and the top row major loop M
2 Swap gate or Replicate gate (round trip line 7
). Incidentally, when the connecting gate 7 is a replicate fighting gate shown later, each of the major loops M1 and M2 is usually replaced with a so-called major line in which the return portions M/ and M are omitted. Also,
Each major loop (line) M1, M2 is equipped with a bubble generator GEl, GE2 and a bubble detector DE1, DE2. Therefore, the operation mode of the connection gates 6 and 7 between each loop or each transfer path as described above is controlled by whether or not a current is applied to the gate control conductor across the gate and its direction. It is.

This 5 is also true for gates for magnetic bubble memory chips other than the two-layer conductor film multi-segmented chip gate illustrated here. The small loops Mj-1,i and Mj,i(j''-2, 3,...)
..., k; i = 1, 2, ......, n), and the 7-swap mode in which information is exchanged with each other by connecting them, and the loop in which information is propagated within each loop instead. One of the seven internal propagation modes can be selected. When all the swap gates are set to the former mode, the small loops belonging to the same column 1 operate equivalently as one minor loop Mi. Such a swap gate was developed by the applicant in Japanese Patent Application No. 55-119.
The application is pending as No. 206 (Unexamined Japanese Patent Publication No. 206).
The details are given in the specification, but the small loops m and 2Jmj-1 (j-2, 3 ,...
..., k; the corner portions of row number 1 (omitted as it can be a staggered row) are connected to each other by a pair of crossed opening patterns 2a and 3a, and the lower edge of each opposing hole is connected to the magnetic field of each loop corner portion. The bubble capture point Pl, P2; P/, P2''.

In FIG. 3, the opening pattern of the first layer conductive film 2 is shown with diagonal lines. Each transfer path or small loop M connected by this swap gate cross opening pattern pair
As is well known, the opening patterns 2b and 3b are formed in the first and second layer conductor films with a predetermined offset relationship, and the bottom of each hole is a magnetic bubble trapping point. P1~P
4, P/~P4'.

Since the present invention is not an invention of the gate structure itself, a detailed explanation of the operating principle will be omitted, and the operation of this swap gate itself will be explained below. By applying an alternating current with
, B'' are the capture points of the respective transfer paths or small loops Mj, mj-1 → P1 → P2 → P3 → P4 → P1...,
→P/→P2''→P3''→P4'→P/... These bubbles cross the opening pattern pair 2a.
When reaching the trapping point Pl, P/ under the edge of the hole at both ends, the gate control conductor 8, which is in a planar overlapping relationship with the first and second layer conductor films 2, 3, is exposed to the next trapping point P2 in the same loop. , P (between PlP2, P/-P2'), there is a bubble repulsion point,
Between the capture points P2' and P2 of other loops (P1-PJ, P
/-P2), when a current is applied to create a magnetic potential distribution that creates a bubble trapping point or attraction point, each bubble B, B'' is transferred to the other small loop, resulting in a simultaneous alternation operation, that is, a swap operation. occurs, and information is exchanged between the transfer path or small loops Mj, mj-1.On the other hand, conversely, the acquisition points P1-PJ,
When a current is passed through the gate control conductor 8 such that a repulsion point is created between P/-P2, the propagation action within each small loop, ie, the gate remains closed. In some cases, the gate control conductor 8 may be supplied with current only when it is in one of the modes; slot 4,
It is composed of a pair of reciprocating control conductor members 8a and 8b that face each other with 5 in between and extend laterally (as shown by the imaginary line 8c, the ends are connected to each other and the current flows in opposite directions in the parts facing each other). It is normal to Further, as shown in the fourth figure, each conductor is covered with an insulating layer 9. Similarly, when the gate operation mode is determined by the gate control conductor 8, there is a replicate gate (Fig. 5) which is often used as the connection gate 7 mentioned above (Japanese Patent Application No. 55-11).
There are also transfer gates (Fig. 6), which do not use slots 4 and 5.

Similar constructors will be explained using the same reference numerals as before.
First, at the replicate gate, each acquisition point J of one transfer path m (generally a minor loop) is sequentially → P1 → P2
→P3→P4→... The bubble that has progressed in the parallel pattern pair 2c, 3c cut out by the slots 4, 5,
When the gate control conductor 8 (
When a current pulse is applied to expand a bubble to the reciprocating conductor members 8a and 8b (generally also consisting of reciprocating conductor members 8a, 8b), this bubble is located under the edge of the opposing hole of the same pattern 2c opposite to the capture point P1, and It expands so as to straddle between the capture point P/ belonging to Mj-1 (generally a major loop or line), and maintains its size according to the current phase to the next first and second layer conductor films. Next capture point P2, P/
At that time, when a current pulse is applied to the gate control conductor 8 to generate a magnetic field in the direction of extinguishing the bubble, the stretched bubble is divided approximately in the middle, and each loop has a single current pulse. One bubble after another is generated.

Therefore, in the next sequence of driving current to the first and second layer conductor films, each bubble advances through the respective loops from P2 to P3 and from P2' to P3'. This gate thus has the advantage that it contributes to faster operation of the entire chip since it is not necessary to return the source information to its original memory location since the information can be multiplexed. The transfer gate shown in Figure 6 is
Since it is the oldest, there is no slot, and the cross opening pattern pair 3a, 2a and the gate control conductor 8 (conductor members 8a, 8
There is b). The operation of this gate is to apply a current pulse to the gate control conductor when the bubble that has progressed through one loop m comes to the bottom of the hole edge P2 of J one side 3a of the crossed aperture pattern pair, and to Instead, it generates a magnetic potential that guides the bubble toward the next point PI of the other loop Mj-1.

However, this gate is inconvenient because information cannot be exchanged simultaneously with each other. The above is an example of a gate in a two-layer conductor film current-driven magnetic bubble memory chip.
Some magnetic bubble memory chips with other operating principles also require a gate control conductor to select the operating mode of the gate.

Therefore, in a memory chip that requires a gate control conductor, for example, devices that require current to flow in the same phase or in the same direction are often connected in advance when the chip is completed.

For example, the gate control conductors 82 to 8 corresponding to m1 to M6 among the small loops connected by the swap gates mentioned above.
If only the gate control conductors 82, 84, 86 for even-numbered gates and those 83, 85 for odd-numbered gates are taken up and shown in FIG.
4, 6, L3, and 5, and are constructed so that the required gate control current described above flows between pads P2 and P6, and between pads P3 and P5 at both ends, respectively.

The reason why these are divided into odd and even groups is that in the illustrated configuration, the timing of clear information propagation is shifted by π between gates, and the gate control conductor between one row (that is, on the slot) is 8j (j=2, 3,...
k) serves as a common control conductor for the swap gates of each column 1 (1-1, 2, . . . , n). Therefore, in such a conventional configuration method, for example, the small loop M2 in the second row,
If you want to use the gate control conductors 82 and 83 independently from the others in order to operate only i (1 = 1, 2, ..., n) independently, please This could not be done after forming the series connection lines L24 and L35 in the REIT, and in the end, a new chip had to be made to accommodate this desired logical configuration. This resulted in defects (1) and (Ji).

The present invention has been made basically with the main purpose of overcoming the lack of distribution and the lack of flexibility or adaptability associated with changes in the logical configuration of conventional chips.

To summarize the present invention, the present invention can also be used when connecting gate control conductors with connection lines according to the logic configuration initially determined at the chip manufacturing stage, and when it is desired to disconnect the gate control conductors later according to the change in the logic configuration. The purpose is to provide a chip that can quickly respond to requests for chip configuration changes from users. .

This is also rational from the manufacturer's point of view, as it facilitates mass production using the same process. Each embodiment of the present invention shown in FIG. 7 and subsequent figures will be described below.

The embodiment shown in FIGS. 7 and 8 is a two-layer conductive film current-driven multi-division magnetic bubble memory chip described in accordance with FIGS. The connecting gate 7 between the loop and the first and second major loops or the lines M1 and M2 is an example of application of the present invention to a memory chip that is a swap gate or a replicate gate.

In this example, the odd gate control conductors {81,8
3, .
=1,3,...,k-1) and Fjj+2(
j-2, 4, . . . , k-2) (k may of course be selected as an odd number).

In this case, each gate control conductor 8j (j-1, 2
, ..., k+1) reciprocating conductor members 8a, 8b
Connecting pads Pj' and Pj to external circuits are attached to the terminals of the terminals, respectively. FIG. 8 extracts only some gate control conductors and shows their relationship including phase lines and connection pads in a perspective view. Even if it is made of the same material as the phase line, it may be formed into a thinner material to have a higher resistance, or only this phase line portion may have a lower melting point.

The point is, for example, if you want to melt down the phase line Fjj+2 in Figure 8, all you have to do is apply a relatively large current between the connection pads Pj' and P,+2 to break this phase line part. Yes, and this in itself does not interfere with the arbitrary use of existing technology.

In this embodiment as well, the gate control conductor groups are classified into odd and even groups, but this is because, as mentioned earlier, the timing of information propagation differs by π between adjacent gates.

Therefore, if this propagation timing shift can be eliminated by improving the gates or using other configuration methods, transfer patterns, etc., all the gates may be connected in series. In the illustrated example, in order to cause the odd-even type to operate in a dependent manner, it is sufficient to shift the timing of gate current application by π. In the memory chip incorporating the phase line in this way, the user can select various logical configurations ranging from FIGS. 9A to 9F by blowing out the phase line at key points.

However, for the sake of simplicity, the gate control conductor is indicated by a single solid line 8, the gate drive circuit that operates independently is indicated by ◎, and the gate drive rotation that operates dependently is indicated by O.

Further, the gate control conductor is simply referred to as a gate. Figure 9A shows
Phases Fk-1 and k+1 were fused to separate gate 8k+1, and the other odd-numbered gate 1 drive circuit 11 drove the even-numbered gates with gate 1 drive circuit /, and 11 and I/ were operated in a dependent manner. This is called a single loop method.

Although this method requires a long access time, all data can be stored serially, so it is suitable for use similar to magnetic tape. B in the same figure further shows the phase Fl3.
The gate 81 is made independent by fusing the gate 81.
is driven by the gate drive circuit 12, the other odd numbered gates are driven by 13, the even numbered gates are driven by 13", and 13 and 13" are operated dependently. This method is widely used because it is much superior to the method shown in Figure A in terms of operating speed.

In the figure C, the method B in the figure has 8k+1 gates added, and the gate 81 is driven once by the gate drive circuit 14, and 8k+1 gates are added.
+1 is driven by 6 and the remaining odd gates are driven by 15''
The even gates are driven by 15, and gates 5 and 15' are operated in a dependent manner.

This is a chip configuration method called a two-measure one-way system, and because it has two input/output ports on the same chip, the access time is reduced to half that of the configuration shown in Figure B, and it is superior in performance. However, the fields of application are almost the same. D in the same figure is
Fuse the phases Fl3, F24, y-ra Fk-1, and separate the gate 8k+1,
The entire gate is {81}, {82}, {83, 85,...
...8k-1L and {84, 85, ...
8k}, and each gate drive circuit 17
, 18, 19, and 197, and 19 and 19'' are operated dependently.

This is called an on-chip cache system, in which the minor loop is divided into two large and small loops, and the smaller one is used as a cache. In this chip, by storing frequently used information in small loops, the minor loop length can be made equivalent to the cache loop length.
Performance is significantly improved compared to the C configuration. Therefore,
This chip is suitable for fields that require high speed. In addition, in this chip, the two-layer conductor film constituting it is
Instead of the conventional type shown in the first and second drawings, as shown by the imaginary line 10 in Fig. The transfer path drive circuits Vll and V1/, Vl2 and Vl2', and V
It is also possible to drive by l3 and Vl3'.

In this case, current needs to be applied to each region only when accessing the information contained therein, which reduces the frequency of driving the minor and loop regions, which consume a very high proportion of power, and reduces the power consumption from the chip. The amount of heat generated is significantly reduced. Even with such a conductor film configuration, the number of transfer path drive circuits is increased, and both the configurations shown in FIGS. E in the same figure) F11
fuse Fl, 37Fk-1, k+1, gate 8k+
1 and the other gates {81L{82,8
4,...,8k), and {83,85,...
.

This chip can perform advanced data handling functions on-chip, such as exchanging stored information for each program, inserting new data, and deleting data that is no longer needed, so high functionality is required. This is a chip construction method suitable for various fields. In Figure F, gate 8k+1 is added to the configuration of Figure E, and the entire gate is {
81}, {82, 84,..., 8kL{83,
85,...,8k-1 }, and {8k+1
}, and each gate 1 drive circuit 1
3, 115 and 116 independently of each other, and is intended to improve the performance of the configuration shown in Figure E.
The fields of application are almost the same.

The above explanation was based on the configuration shown in Figures 7 and 8 (a configuration in which two pads are arranged for each gate and all the pads are connected in phases), but in this chip, the number of divisions (as shown in the figure) is In the case of , the number of pads increases with k+2), so
If there are too many of these, problems will occur in implementation.

Therefore, the number of pads must be determined by taking into account the type of chip desired to be realized and the trade-off between implementation costs. For example, if only the chips shown in FIGS. 9A to 9F are to be implemented, the configurations shown in FIGS. 7 and 8 are not necessarily required, and the second embodiment shown in FIG. 11 is sufficient. In this chip, regardless of the number of divisions, the number of gate drive pins is P1, P/;P22P2l;''1-8;P5
Ten pieces of LA P5', f1-'s are Fl3 LA F2472yFk
-1, k+1, which is a small and realistic value.

Even with this configuration, the phase Fl32F24y7? Fk-1
, k+1, it is clear from the above that the above chip configuration can be arbitrarily adopted.

By the way, until now, only the case where the gate control conductors are connected in series has been described.

However, in recent years, as the density of information has increased, that is, the bubble diameter has become smaller, the line width of each chip component has become smaller, and the resistance value has become extremely large. Problems may arise with gate control conductors. Under such circumstances, connecting several gate control conductors in series will further aggravate the problem. Therefore, in such a case, parallel connection may be considered as shown in the third embodiment shown in Figure 12.

In this embodiment, odd and even gate control conductor groups are connected in parallel, and phases Fj,j+2 (j-1, 2, ..., k-1) are connected in parallel connection lines. It incorporates. Therefore, even if the number of gates that are driven simultaneously increases, the combined resistance value will not increase, and the pads on the ground side (for example, P/, P2'') can be shared between odd and even numbers. There is also the advantage that the number of pads can be reduced compared to the previous embodiment of diameter connection.
If it is sufficient to selectively realize each of the logical configuration chips shown in Figure F, then for the same reason as stated above in conjunction with Figure 11, it is possible to leave out the three phases Fl, 3, F2, 4, Fk-1, and k+1. The other phase portions are connected to normal connection lines Lj, j+-2 (j=3, 4, . . . , as in the conventional example shown in the first figure).
k-2), and the pad is also P1ゞP4raP/YP2ZPk
-1ゝProduction can be simplified by using a chip in which Pk-1 is left and the others are omitted.

As is obvious from the above description of the embodiments, from the point of view of the present invention, which is to connect gate control conductors with a fusible phase line, it is possible to apply other pad arrangements, gate-to-gate connection methods, and chips with conductor film structures. The present invention is also applicable to the following.

As detailed above, according to the present invention, it is possible to provide a so-called adaptive structure type 7 chip whose configuration can be changed depending on the application, so that the user can easily select the chip (logical configuration selection).
In addition to increasing the degree of freedom in manufacturing, we can fully expect cost reductions due to mass production effects.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a two-layer conductor film current-driven multi-division magnetic bubble memory chip having a conventional gate-controlled interconnection line between conductors to which the present invention can be applied, and FIG. 3 is a plan view schematic diagram of a swap gate as a connection gate between transfer paths used for chip offsetting in the configuration shown in FIGS. 1 and 2; FIG. 4 is a sectional view taken along the line in FIG. 3;
The figure is a schematic plan view of a replicate gate as another example of a connection gate, FIG. 6 is a schematic plan view of a transfer gate as another example of a connection gate, and FIG. FIG. 8 is a perspective view of essential parts of the embodiment shown in FIG. FIG. 10 is an explanatory diagram of a chip in which a two-layer conductive film is divided into regions, and FIGS. 11 and 12 are schematic configuration diagrams of the second and third embodiments, respectively. In the figure, 1 is a substrate film that carries a magnetic bubble, 2 and 3 are first and second layer conductor films, 4 and 5 are slots, 6 and 7 are connection gates,
8 is a gate control conductor, F is a phase line, P is a pad,
It is.

Claims (1)

[Claims] 1 A magnetic bubble memory chip having a plurality of connecting gates connecting magnetic bubble transfer paths, each of which has a gate control conductor for controlling its operation mode, and the connection between the gate control conductors can be fused. A magnetic bubble memory chip characterized by using fuse lines.