JPS592992B2 - Input/output method in magnetic bubble memory tube - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved input/output method for improving the performance of magnetic bubble memories, particularly double-layer conductor magnetic bubble memories.

Conventional double-layer conductor magnetic bubble memory is fast, nonvolatile,
It has advantages such as high reliability and is seen as promising as high-speed auxiliary memory, file memory, etc.

However, since the moving speed of bubbles, which are information carriers, has an upper limit that is determined mainly by the bubble material, when a higher data transfer rate is required, a large number of chips must be placed side by side and driven simultaneously. Must be. However, if this is done, the number of transfer path drive circuits and heat generation from the device will increase, which is disadvantageous because the cost associated with deviceization will increase. The present invention was basically made in view of the above points, and by focusing on the input/output operation timing of a two-layer conductive bubble memory, it is possible to realize , which aims to achieve a data transfer rate that is substantially higher than that of the 15 conventional devices.

The transfer path, bubble generator, and detector constituting the chip of the two-layer conductor bubble memory are well known, but prior to describing the embodiments of the present invention, the schematic structure and operation will be explained using FIGS. 1 to 4. Add.

The transfer path is on the carrier 1 of the magnetic bubble B as shown in the first diagram.
A first layer conductor film 3 is formed with a spacer 2 interposed therebetween, and a second layer conductor film 5 is provided thereon with an insulating spacer 4 interposed therebetween.
The first and second layer conductor films 3 and 525 each have a series of opening patterns 3a, 5a at a constant pitch along the direction in which the bubble B is to be transferred (arrow T). ...
...... are arranged, and the pair of 3a and 5a is 1
Form the bit. These opening patterns are arranged in a constant overlapping relationship along the transfer direction, as shown by virtual lines 303a' and 5a' projected onto the carrier 1 in FIG. Although each layer 1 to 5 is shown in an exploded perspective view in FIG. 1, the adjacent layers are in close contact with each other in the vertical direction (arrow A). In addition, in FIG. 1, the opening patterns 3a, 35
Although 5a is shown as an ellipse, it may have other shapes, such as a rectangle, a rhombus, a hexagon, or other shapes. Positive and negative current pulses 1 and 13 perpendicular to the propagation direction T9□- are applied to the first layer conductor film 3 constituting the transfer path, and current pulses 12 and 14 in the same positive and negative directions are applied to the second layer conductor film 5 by the arrows shown in the first diagram. By applying the current phase 1712'13'1 of the bubble pump 4 in the direction of, for example, the sequence shown in FIG. 2A,
4y11......P on the transfer path
It propagates in the order of 1→P2→P3→P4→P1→...

Therefore, by applying one cycle of current, ie, current pulses 1 to 4, the bubble moves by one bit (one step). The bubble generator consists of a hairpin-shaped conductor 7 as shown in the third figure, and generates bubbles by a local vertical magnetic field generated when a current pulse is applied to the conductor 7.

The timing of this current pulse application is determined by the relative arrangement of the aperture pattern and the hairpin-shaped conductor 7. In the case of the arrangement shown in FIG. 3A, the timing of IGl in FIG.
At the timing of 2, in case of C, at the timing of IG3,
In the case of and D, the timing must be IG4. Finally, the detector will be explained. Normally, bubbles are detected using the property that the resistance of a permalloy thin film changes depending on the bubble's leakage magnetic flux (magnetoresistive effect). This resistance change is extracted as a voltage change outside the chip,
In order to increase this voltage, the detector is elongated and elongated, and along with this, the transfer path opening pattern near the detector is also oriented perpendicularly to the bubble propagation direction T, as shown in Figure 4, 31, 5ff'. It takes on a stretched shape. The phase of the detection signal is determined by the relative arrangement of the detector and the aperture pattern.
When the detectors are placed at the positions Dl, d2, d3, and D4 shown in Figure 4, the relative phase of the detection signal output with respect to the transfer path drive current is VDl, which is schematically shown in Figure 2C.
, VO2, VO3 and VD4.

In addition, in FIG. 4, for the sake of simplicity, only the lead wire 6 is shown added to the detector placed at d1, but of course, the lead wire 6 is shown attached to the detector placed at D2,
It is assumed that similar lead wires are connected to the detectors placed at d3 and D4. The above is an overview of the transfer path, bubble generator, and detector, which are the main components of a memory chip. In order to perform memory operations, it is necessary to appropriately combine these components to construct a memory chip.

FIG. 5 shows an example of an existing typical chip configuration. This is called a major/minor/loop configuration, with a generator G serving as an input port for information, a detector D serving as an output port, a major/loop M connecting the input and output ports to the storage area, and information It consists of a minor loop m1 that stores and holds information, and a transfer gate Tf that controls the exchange of information between the major loop and the minor loop. During writing, a series of information written by the generator G propagates through the media loop (by applying a transfer path drive current at a predetermined period), is lined up along the transfer gate TfIIC, and is then transferred by Tf. Stored in parallel in many minor loops (naturally resulting in serial-parallel conversion).

On the other hand, when reading, a predetermined number of steps are propagated in parallel on each minor loop.
A group of information arranged in a line facing the gate Tf is Tf
After being output onto the measure loop (naturally resulting in parallel-to-serial conversion), the signal is read out bit by bit by the detector D. After the readout, these pieces of information continue propagating in the same direction again and are stored at the original position on the minor loop via the transfer gate Tf. Therefore, if the number of input and output ports is increased to n and a rational operation is achieved, even if the speed at which information moves within the chip is constant, the speed at which information is transferred between the chip and the outside,
That is, it should be possible to increase the data transfer rate by n times, and by doing so, it is possible to input and output data to and from the chip at a high speed higher than the transfer path drive frequency.

Therefore, the present invention also provides such input and output operations in two-layer conductor devices, especially in multi-segment chips (Japanese Patent Application Nos. 55-101635, 148460, and Japanese Unexamined Patent Publication No. 1988-1981), which the present applicant is currently applying for. It has been improved to make it possible. To summarize the present invention, a plurality of input and output ports are formed on one chip, and their operation timings are shifted by a predetermined phase to operate in parallel. The relative positions of the detectors and generators and the transfer path opening patterns are shifted from each other, or the relative positions of the opening patterns in the first and second layer conductors near the plurality of detectors and generators are reversed. do.

In this way, the number of bits input and output from the chip per cycle of the transfer path 1 drive current is multiplied by n (n is the number of input and output ports per chip), improving the data transfer rate. . In the first embodiment of the present invention shown in FIG. 6, the conventionally constructed chip shown in FIG. Detector D1 placed at position d1 in Figure 4, generator G2 shown in Figure 3B and detector D2 placed at position D2 in Figure 4 for C2 block.
The C3 block includes a generator G3 shown in Figure 3C and a generator G3 shown in Figure 4.
In addition, the C4 block has a generator G4 shown in Figure 3D and a detector D4 located at position D4 in Figure 4.

In this case, the input data (forming a pulse train) Vi is the seventh
A logic circuit consisting of an AND circuit 10 as shown in FIG.
(pulses supplied from the chip's leg propulsion circuit, each in phase with 1G1, IG2, IG3, and IG4) are divided into four, and then amplified by the amplifier 11 to a predetermined signal level. . Figure 7B shows the input data Vi
The example shows the case where 10110110101...... is input as the output from the logic circuit.

1, IG2, 16 and I.

4, it can be seen that the period is four times that of the input data, that is, the frequency is reduced to 1/4.

That is, in this chip, each block Cl, C2, C
It can be seen that data can be input at four times the speed at which each constructor in C.3 and C4 is operating. on the other hand,
Readout, ie, output of data from the chip, is a signal taken out from each detector Dl, D2, D3, and D4, as shown in Figure 8A.

1, V02, VD3 and VD4 are set to predetermined voltage levels D1'', VD2'', D3'' by an amplifier (sense amplifier) 12.
and D4'', and then synthesized in the 0R circuit 13 (in this case, D1 and D3, and D2 and D4
It is also possible to configure a bridge using the following, and since this reduces the number of sense amplifiers by half, such a configuration method is effective in simplifying peripheral circuits and reducing costs.

). As a result, as shown in Figure 8B, the data transfer rate of the entire chip is quadrupled. That is, according to the first embodiment of the present invention shown in FIG. 6, it is possible to obtain a data transfer rate that is four times the operating speed of each component in the block when inputting and outputting data from the chip. Note that the access time is not shortened in this embodiment. Subsequently, the present invention was applied to a multi-segmented chip (Japanese Patent Application No. 55101635, 1484).
60), this multi-divided chip has a part of the left end or a part of the right end at the same position in the two-layer conductor film constituting the transfer path and the return conductor film. By alternately arranging the slots (30 and 31 in Figures 13 to 15) that are left uncut for energization, a global meandering conductor is formed to reduce the drive current.・Since the loop is divided into small loop groups by slots, there is a swap that connects the loops.
Gate (Japanese Patent Application No. 119206/1986,
No.) and Replicate Gate (Patent Application No. 1986-11)
No. 9205) is an essential component.

Therefore, in the following, before explaining the multi-segmented chip, we will first give an overview of these gates using specific examples. However, the gates used in the present invention are not limited to the gates described below, but may be gates that have equivalent functions, such as a swap gate having seven modes of inter-loop propagation and seven modes. - Gates and replicate gates with information replication functions may have other shapes, arrangements, structures, etc. The swap gate has a configuration as shown in Figure 9A, with the gate control conductor 20
Depending on whether or not a current is applied to the transfer path or small loop Mj-
1 and Mj and exchange information with each other; and 7 modes in which each loop Mj-1, mj
One of seven intra-loop propagation modes for propagating information within the loop can be selected.

If the swap gate is set to the always swap 7 mode, the two small loops connected by this gate will merge into one larger loop. Note that, in the following, the opening pattern shape is assumed to be rectangular. The swap gate consists of small loops Mj-1 and Mj-1 facing each other with slots 30 and 31 cut out in the first and second layer conductor films 3 and 5.
The corner portions of j are a pair of crossed opening patterns 3b and 5
b, and the lower edge of each opposing hole is the transfer path or small loop Mj-1. Magnetic bubble trapping point Pl2P2 of Mj:
P/F Pl (P1 and P/ and P2 and P2'' are respectively capture points at the same time).

In FIG. 9, the opening pattern of the first layer conductive film 3 is shown with diagonal lines for differentiation. Each of the transfer paths or small loops Mj-1, mj connected by the swap gate cross-opening pattern pair is formed by opening patterns provided in the first and second layer conductor films with a predetermined offset relationship, as described above. vs. 3a, 5a
When a transfer path driving current is applied to each conductive film, the current has opposite polarity in adjacent regions with the slot as the boundary, so the magnetic bubbles formed under the edge of each hole are trapped. Points P1 to P4, P/ to P4' (Pl
, P2, P3 and P4 respectively have P/, PI, Pf
and P4' correspond to each other, and these corresponding pairs simultaneously become capture points) as shown in the figure. When the bubbles in the transfer path or small loops Mj, mj-1 reach the trapping points Pl, P/ under the hole edge of the cross opening pattern 3b, they are flat with the first and second layer conductive films 3, 5. When the gate current IG is applied to the overlapping gate leg conductors 20 at the timing shown in FIG. Information is exchanged between Mj-1. To explain the swap operation in more detail with reference to FIG. 10, the bubble B in the upper loop and the bubble B' in the lower loop with the slot as the boundary move between P4 and P1 and between P4' and P1 at the corner. (The position of the bubble trapping point is the same as in FIG. 9A). If the gate current pulse IGl shown in FIG. 9B is applied in the direction of enlarging the bubbles, bubbles B and B' will be enlarged. The state shown in Fig. A-2 (corresponding to 2 in Fig. 10B on the time sequence) is reached.

Subsequently, if a gate current pulse IG2 of opposite polarity is applied at the timing shown in Figure 9B between the bubble trapping points formed at P2 and P2', bubbles B and P2' will be trapped at P2, respectively.
', rapidly shrinking while moving to P2 (state of A-3;
(corresponding to 3 in Figure B), and finally returns to a stable circular shape (state A4; corresponding to 4 in Figure B). In this series of operations, if there is no bubble in either or both of the corresponding positions of the upper and lower loops (i.e., if the information 'O' is retained), the position of B or B' is By considering the virtual existence of the bubble 2 in the sky, it can be confirmed that the bubble 7 in the sky moves in the same way as above.As a result, as mentioned above, the bubble B in the loop above moves. The bubble BI of the lower loop moves to the upper loop at the same time, and information is exchanged between the loops, that is, a swap operation is performed.On the other hand,
Unless a gate current of 1 G is applied, each bubble will not move across the slot, resulting in a propagation operation within each transfer path or small loop. Generally, as shown in FIGS. 9 and 10, the gate control conductor 20 of this swap gate is composed of a pair of reciprocating conductor members 20a and 20b that face each other with slots 30 and 31 in between and extend laterally. It is normal to do so. Next, the replicate gate will be explained, with components similar to the swap gate being denoted by the same reference numerals.

On one transfer path or small loop Mj → P1 → P2 → P3
→P4→・・・・・・ Parallel opening pattern pair 3c, in which the bubbles that have progressed are cut out at the slots 30 and 31,
5c, when the gate control conductor 21 (generally also reciprocating conductor members 21a, 21b) is sealed to the bottom P1 of the hole edge.
When a current 1G1 is applied in the direction of enlarging the bubble at the timing shown in Figure 11B, the bubble B will straddle between the capture point P1 on Mj and the capture point P/ on the other transfer path M. (state of A2 in Fig. 12A; 12th
B) corresponds to position 2 on the illustrated time sequence). This bubble B moves to the next capture point P2, P2' with this size according to the phase of the transfer path drive current, but at this time, a current 1G2 is applied to the gate leg conductor 21 in the direction of extinguishing the bubble. If the voltage is applied at the timing shown in Figure 11B, the stretched bubble B will be divided into two near its center (the state of A-3 in Figure 12A: corresponds to position 3 on the time sequence shown in Figure 12B). . Since these two parts naturally return to a stable circular shape, bubbles B and B' appear on each transfer path (Fig. 12A-A-
4 state: corresponds to position 4 on the 12B illustrated time sequence). If there are no bubbles initially, no new bubbles will be generated by the above sequence.
That is, with this gate, it is exactly the same as the loop m above)
) The same information pattern J is duplicated on the lower loop M. As we have seen above, this gate allows information to be duplicated, and when reading it, the source information can always be kept in its original storage location, so there is no need to return the information to its original location after the operation is completed. This has the advantage that memory operation becomes more efficient, and when a malfunction occurs in the detector and information is lost,
It has the advantage that it can be reread by duplicating the source information again. An embodiment in which the present invention is applied to a multi-segmented chip is shown in FIGS. 13-15.

Both of these have two input and output ports on one chip, but the aperture pattern arrangement in the input/output row area including these two input and output ports is such that the propagation directions are opposite to each other. In addition, the relative arrangement of the generator, detector, and aperture pattern is set such that the operation timings of the two input/output ports are shifted from each other by π. Specifically, this is achieved as follows. First, for the input port, generator G
The conductor and opening pattern arrangement constituting / is as shown in 3A, while the hairpin conductor constituting GI is arranged as 3D
After the illustrated arrangement is made, the transfer path opening pattern arrangement is changed to that shown in FIG. 3, with the openings in the first layer conductor film and the openings in the second layer conductor film interchanged. Regarding the output port, similarly, the detector D is placed at the position d1 in the fourth figure, and the aperture pattern in the vicinity thereof is arranged as shown in the fourth figure. After placing it at position D4, assume that the opening pattern arrangement is as shown in Fig. 4, with the openings in the first layer conductor film and the openings in the second layer conductor film swapped.As a result, the operation between the two input or output ports is changed. Since the timing is shifted by π,
Similar to the first embodiment, it is possible to obtain a data transfer rate that is approximately twice that of the conventional example shown in FIG.

Note that all of the embodiments other than the embodiment shown in FIG. 14 consist of two mutually independent major and minor configurations, but in the example shown in FIG. It is also possible to adopt a similar configuration. Furthermore, in the embodiments shown in Figures 13 to 15, the input/output row area and the plurality of row areas forming the storage area are continuous conductors, but it is also possible to divide these and drive them separately. . In this case, the power consumption of the whole chip,
That is, there is an advantage that heat generation on the chip can be reduced.
In addition, although the above explanation is based on an example in which the number of conductor film row areas is 70%, this number may be arbitrary, and in that case, similar measures can be taken for the relative arrangement of the bubble detector and generator and the transfer pattern, etc. The same effect can be achieved by applying In addition, although the input/output control peripheral circuits shown in Figures 7A and 8A have been explained as examples, other circuits may be used as long as they have similar functions, such as series-parallel, parallel-serial converters, etc. or some other method may be used. As detailed above, according to the present invention, a higher data transfer rate can be achieved even if the transfer path drive current and bubble material have the same frequency as conventional ones.
It is now possible to adequately handle applications that require high speed, and the field of application and use can be expected to expand.

[Brief explanation of drawings]

Figure 1 is an exploded perspective view of the basic components of the two-layer conductor film magnetic bubble transfer path, and Figures 2A, B, and C are the drive current sequence of the first illustrated transfer path, the drive current of the bubble generator, and the detector, respectively. 3 is an explanatory diagram of the relative arrangement of the hairpin conductor that constitutes the generator and the transfer path opening pattern, and Figure 4 is an illustration of the permalloy thin film that constitutes the detector and the opening pattern near the detector. FIG. 5 is a diagram of the configuration of a conventional two-layer conductor bubble memory chip; FIG. 6 is a schematic configuration diagram of the first embodiment of the present invention; FIG.
, B is a configuration diagram of an example of the input section control circuit of the first embodiment and a time sequence diagram of signal pulses of each part thereof.
Similarly, Figure B is a configuration diagram of an example of the output section control circuit of the first embodiment and a time sequence diagram of the signal pulses of each part thereof.
Figures A and B are a configuration diagram of an example of a swap gate and a gate current pulse sequence diagram; Figures 10A and B are explanatory diagrams of the operation transition of the swap gate shown in Figure 9 and the corresponding times on the time sequence; Figures 11A and 11B are diagrams illustrating the configuration of an example of the replicate gate and its gate control pulses, and Figures 12A and 12B are diagrams illustrating the operation transition of the replicate gate shown in Figure 11 and the corresponding times on the time sequence. , FIG. 13 is a schematic diagram of the second embodiment of the present invention, FIG. 14 is a schematic diagram of the third embodiment of the present invention, and FIG.
The figure is a schematic configuration diagram of a fourth embodiment of the present invention.

Claims (1)

[Claims] 1. An opening pattern formed in a two-layer conductor film on a substrate film carrying magnetic bubbles constitutes a transfer path for the magnetic bubbles, and a storage area is formed by the transfer path. In this input/output method, the storage area is provided with a plurality of input ports and a plurality of output ports, and the operation timings of the input ports and the output ports are shifted by a predetermined phase. An input/output method in a magnetic bubble memory chip characterized by operating a port and a plurality of output ports in parallel.