JPS5930020B2 - Parallel operation inverter control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a parallel operation inverter, and more particularly to a control device for a parallel operation inverter that rectifies alternating current from an AC power source and then converts it back into alternating current to obtain stable alternating current power. .

2. Description of the Related Art A power supply device having a configuration as shown in FIG. 1 is generally used as an uninterruptible power supply device for a computer or the like.

That is, AC power from AC power supply 1 is rectified by converters 2 and 3, then converted back to AC by parallel operation inverters 4 and 5, and then connected to switch 6.
and 7, it is supplied to the load 8 as stable AC power. If AC power supply 1 stops, DC power (not shown) from a backup battery or the like is applied to inverters 4 and 5 to ensure power supply to load 8. In the power supply device as described above, converters 2 and 3 and switches 6 and 7 are controlled to start and stop by operating circuits 15 and 16, respectively. On the other hand, the configuration and control of inverters 4 and 5 operated in parallel are as follows. First, one inverter, for example inverter 4
As shown in FIG. 2, six unit inverters 11,
12, . . . 16, and each unit inverter, for example, unit inverter 11, has a group of A and B side thyristors. For example, the A-side thyristor group is composed of main circuit thyristors A11 and A12 and commutation thyristors A13 and A14. During steady operation, each unit inverter operates with a time lag of 300, as shown in Figure 3, and within each unit inverter, for example, the thyristor on the A side operates. By shifting the firing timings of A11 and B-side thyristor Bll by △, the energization width is controlled and the output voltage is controlled. Such control of the inverter is performed using the output of the oscillation circuit 11 as a common ignition signal source shown in FIG. 12 and a firing signal generated by gate signal forming circuits 13 and 14.
According to the above configuration, the firing signals applied to the inverters 4 and 5 are in principle in the same phase, and the actual unevenness and phase difference in the output voltages are caused only by the unevenness of each component. The occurrence is extremely small.

Therefore, parallel operation inverters 4 and 5 during steady operation
The load is divided almost equally between the two. However, the conventional parallel operation inverter control device as described above has the following drawbacks, particularly at the time of startup.

That is, if you start up inverters connected in parallel one after another, or if one inverter is supplying power to a load and you try to start up the other inverter,
Since the phase control circuit 12 is shared by both, the firing phase of only one cannot be changed. Therefore, as shown in FIG. 4A, the energization width of the activated inverter remains wide, and the output voltage increases. Therefore, the current flowing into the inverter transformer and the waveform improving filter may become excessive, resulting in failure of commutation of the inverter. In order to avoid this commutation failure, it is possible to increase the commutation capacity, but
That is uneconomical. Furthermore, as a conventional method for reliably starting an inverter without increasing the commutation capacity, a method has been used in which the DC voltage applied to the inverter is lowered at the time of starting, thereby suppressing the starting current of the inverter. FIG. 5 is a diagram showing a specific example of the DC voltage control method as described above, and FIG. 6 is an operation time chart of the circuit shown in FIG.

In Figures 5 and 6, T1 when the inverter starts up
First, switches 51A, 51B, and 51C are turned on to apply AC power to the converter via resistors 61A, 61B, and 61C. At this time, the converter output, that is, the input voltage of the inverter increases with a time constant determined by resistors 61A, 61B, 61C1 reactor 70, and capacitor 71, as shown in FIG. When this voltage reaches a time point T2 that is suitable for commutation of the inverter, a gate signal is applied to the inverter, and a time point T2 determined from the converter output voltage and inverter current is applied.
3 and T4, the switches 52A to 52C1 and the switches 53A to 53C are sequentially turned on. in this way,
Since a common phase control circuit 12 is used, a resistor must be inserted on the input side of the converter connected to the inverter to be started, and the inverter must be controlled while controlling the DC voltage. However, it is not preferable to provide a resistor or a switch in the main circuit in terms of device cost and design. In addition, if a phase control circuit is provided for each inverter, startup control becomes easier, but this causes imbalance and phase differences in the output voltages of each inverter during steady variable train operation, resulting in imbalances in load sharing. The drawback is that there is a cross current as well as an equalization. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a control device for a parallel operation inverter using a common control method that can be started without operating the main circuit. The above object is to provide a control device according to the present invention, which includes a main control circuit for commonly controlling the output voltage of each inverter during steady operation, and a unit control circuit provided for each inverter.
When one inverter is started, the unit control circuit provided in the inverter gradually increases the energization width of the inverter's thyristor from a small value to a value determined by the main control circuit, thus controlling the overvoltage of the inverter output that occurs during startup. This can be achieved by doing.

The details of the present invention will be explained below using examples.

FIG. 7 shows an embodiment of a control device for parallel operating inverters according to the present invention. In FIG. 7, oscillation circuits 111, 1
A main control circuit 140 consisting of a binary ring counter 112, a voltage control circuit 113, and a variable delay circuit 114 commonly controls each inverter, and includes a variable delay circuit 115, a starting phase control circuit 116, a switching signal forming circuit 117, a flip-flop 121, 122 and 123, gate signal forming circuits 128, 129, etc.
50 is provided for each inverter and controls each inverter. The operation of the control device configured as described above will be explained using the operation explanatory diagrams of FIGS. 8, 9, and 10.

However, it is assumed that the inverter has the configuration shown in FIG. In the main control circuit 140, first, an output signal S having a frequency determined based on the configuration of the inverter and the inverter output frequency is output from the oscillation circuit 111.

The starting point of the clock signal S is the oscillation circuit 111, the hexadecimal ring counter 112, and the delay circuit 11 of the main control circuit 140.
4 and the delay circuit 115 of the unit control circuit 150, and is given as a phase that is ΔT ahead of the operation start phase (phase of the A signal) of the delay circuit 114 that controls the energization width of the inverter during steady state. In this output signal S, 12 pulse outputs correspond to the period T of the inverter output. Decimal ring counter 112 manually inputted with signal S
From then on, reference signals A and B for synchronously operating the unit control circuit 150 are generated every period T as shown in FIG. The reference signals A and B are shorter than a half period of the inverter output than the change width of the current conduction width for controlling the output voltage of the inverter, and
It is a signal having a phase difference ΔT of 1201 which can be formed by 12. On the other hand, in the voltage control circuit 113, a voltage EC for controlling the output voltage of the inverter is output based on the set value of the output voltage of the inverter and the actual output voltage, and this voltage EC is applied to the delay circuit 114 and the starting phase control circuit. 1
16. Since the delay circuit 114 gives the input signals A and S a delay time △ as shown in FIG. These result in delayed signals D, which are applied to the unit control circuit 150.
This delay amount Δ is provided to the inverter corresponding to the voltage EC for controlling the current conduction width. Next, unit control circuit 1
The operation of 50 will be explained.

The starting phase control circuit 116 generates an output ECU determined by the output voltage EC of the voltage control circuit 113 as shown in FIG. 10 when no starting signal is applied. If a start signal is applied, the output voltage ECU decreases with a time constant required to start the inverter. The output of the delay circuit 115 for such a voltage ECU becomes a signal obtained by adding a delay time △U to the input signal as shown in FIG. A signal F delayed by ΔU from the signal S is outputted as shown in FIG. In this case, the delay time Δ of the delay circuit 114 changes within a certain range because it controls the energization width during steady operation, that is, the output voltage of the inverter that is being operated first. Furthermore, since the inverter to be started later will also be controlled by this Δ when starting is completed, the delay time ΔU of the delay circuit 115 related to the current flow width control factor at the time of starting is shown in FIG. As shown, it is set to have a correlation of Δ and a constant difference Δ0. Additionally, △ and ΔU are, for example, △-△U+△T in order to avoid reversal of the firing signals applied to the A-side and B-side thyristors in the case of the inverter having the configuration shown in FIG.
It is determined based on 180 additional design conditions.

For example, when ΔT is set to 120 as described above, a is set to satisfy the relationship Δ−ΔU×600.

Therefore, the phase difference ΔS between the synchronization signals C and E when the activation signal is applied remains constant even if the voltage EC changes. In addition,
It is assumed that ΔU is saturated at the maximum value ΔT due to the characteristics of the delay circuit 115, and ΔT is the phase difference between the signal A and the signal B determined by the hexadecimal counter 112. As described above, when the activation signal is applied at time TS, the flip-flop 12
2, the output signal H is set to high level in synchronization with the signal E,
As a result, the signal F is output to the AND circuit 125 and the OR circuit 130.
and is applied as a signal K to a gate signal forming circuit 128 via an AND circuit 126, and the output firing signal of this circuit 128 is applied to the A-side thyristor in FIG. on the other hand,
At this time, the output L of the flip-flop 123 is inverted in synchronization with the signal C, so that the signal D is output to the AND circuit 127.
The signal M is applied to the gate signal forming circuit 129 via the signal M. The output of this circuit 129 is the second ignition signal.
The voltage is applied to the B-side thyristor in the figure. Therefore, the time difference between the ignition signals applied to the A side and B side at startup is 8th
As shown in the figure, it is ΔS.

After the start signal is applied, as described above, the output voltage ECU of the start phase control circuit 116 gradually decreases, so the delay time ΔU of the signal F gradually increases as shown in FIG. The time difference between the B-side thyristor and the B-side thyristor gradually becomes smaller than the above ΔS, and the energization width is gradually increased.

Then, the delay time of the delay circuit 115 reaches the saturation value ΔU+ΔT. At time T7, when this point has passed, the signal G is output from the switching signal forming circuit 117, and the output of the flip-flop 121 is inverted at time T8 when it is synchronized with the output signal S of the oscillation circuit 111, and the output J is as shown in FIG. become. Therefore, the signal F is cut off at the AND circuit 125, and the signal S is passed through the AND circuit 124 and the OR circuit 13 instead.
0 and becomes the input signal K of the gate signal forming circuit 128 via the AND circuit 126. Unit inverter 1 in Figure 2
FIG. 11 shows the relationship between the gate firing signals of the thyristors All, Al2, Bll, and Bl2 of No. 1. K from T6
is applied to the gate signal forming circuit 128, and All
A gate firing signal is formed, and at the T6 point of the 7th wave, All
The gate firing signal of Al2 becomes 0ff, and the gate firing signal of Al2 is formed. On the other hand, from the signal of D, the AND circuit 12
The M signal formed through gate signal forming circuit 1
29 to form gate firing signals of Bll and Bl2. For example, the width of the gate firing signal for All is controlled by the ECU so that TA]JS at startup and TA and lB at steady state are gradually increased by △U, so TA
Since there is a relationship of llS>TAllR, as shown in the output P of the unit inverter 11, the energization width Qll at startup is
S and the energization width QllR during steady state are QllS<QllR.

When the startup operation is completed as described above, the time difference between the outputs of the gate signal forming circuits 128 and 129 is changed from ΔS at the start of startup to the time difference Δ determined only by the delay circuit 114. If the energization width is initially small as shown in FIG. 4B and gradually increases to the state shown in FIG. 4A, this time difference Δ is equal to the time difference of the inverter already in operation.

Note that in the explanation of FIG. 8, the time T required for startup is shown for convenience of explanation.
Although 8-T6 is described as a short time, it actually takes the time necessary to start up the inverter.

Further, in the gate signal forming circuit 128, the signal F is changed to the signal S.
In order to prevent malfunctions when switching to the signal S, more reliable operation can be ensured by providing a prohibited region in which no response is made to inputs at time intervals that are sufficiently smaller than the period of the signal S. As is clear from the above explanation, by using the control device for parallel operation inverters according to the present invention, startup can be easily and reliably performed without causing unevenness in the output of each inverter during parallel operation. .

In addition, in the above embodiment, the firing signal to the A-side thyristor of the inverter was controlled to change at the time of startup.
This may be configured to change the firing signal of the B-side thyristor.

Further, the delay time of the delay circuit 115 can be corrected according to the voltage of the AC power supply, the output voltage of the converter, or the output signal of the voltage control circuit 113, and these modifications do not go beyond the scope of the present invention. .

[Brief explanation of drawings]

Figure 1 is a system diagram of a conventional parallel operation inverter, Figure 2 is a specific example of an inverter circuit, Figures 3, 4A and 4
Fig. B is an explanatory diagram of the operation of the inverter, Fig. 5 is a diagram showing a specific example of a conventional converter circuit, Fig. 6 is an explanatory diagram of the operation of a conventional parallel operation inverter at startup, and Fig. 7 is a diagram illustrating the operation of the parallel operation inverter according to the present invention. FIG. 8 shows an embodiment of the control device for the operating inverter.
9 and 10 are explanatory diagrams of the operation of the embodiment of FIG. 7, and FIG. 11 is an explanatory diagram of the operation of the thyristors All, Al2, Bll, and Bl2 of the inverter 11 shown in FIG. 2. Explanation of symbols, 140... Main control circuit, 150.
... Unit control circuit, 111 ... Oscillation circuit, 112 ... Decimal counter, 113 ...
...Voltage control circuit, 114, 115...Delay circuit, 116...Start phase control circuit, 117
...Switching signal forming circuit, 121, 122, 12
3...Flip-flop, 128, 129...
...Gate signal formation circuit.

Claims (1)

[Claims] 1. In a parallel operation inverter control device in which a plurality of thyristor inverters are connected in parallel to supply AC power to a load, the output voltage of each of the above inverters during steady operation becomes a predetermined set voltage. A main control circuit for commonly controlling the thyristor energization width of each of the above inverters, and a main control circuit provided for each of the above inverters to start the thyristor energization width of the inverter when starting any one of the inverters. The unit control circuit has a function of making the energization width smaller than the energization width during steady operation determined by the main control circuit and gradually increasing the energization width as time passes until the energization width reaches the energization width during steady operation. A control device for a parallel operation inverter, characterized in that: