JPS5931087B2 - Control method of terminal control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a control method for a terminal control device, in particular, a terminal control device that mediates data transfer control between a plurality of terminal devices and a host data processing device. It is configured to have multiple terminal interface circuits corresponding to each grouped set, and the data reception for each terminal interface circuit is combined into one and interrupts the host data processing device. The present invention relates to a control method for a terminal control device that reduces the overhead of the host data processing device.

A conventional terminal control device has one terminal interface capable of performing interface processing with n terminal devices, for example, corresponding to n terminal devices.

For example, when receiving data from one terminal device, the terminal control device transfers the data to the host data processing device, interrupts the host data processing device, and receives the processing result from the host data processing device ( e.g. response)
was received and notified to the terminal device. For this reason, each interrupt typically includes 05 overhead time, which is several times the actual processing time.
Despite improvements in the processing speed of the hardware of the host data processing device, there has been a problem in that the overall processing speed has not improved. SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned problems, and is configured so that data reception from a plurality of terminal devices is so-called integrated into one and interrupted into a host data processing device, thereby effectively overcoming the above-mentioned problems. The purpose is to reduce head time.

To this end, the terminal control device control method of the present invention is such that each of one or more terminal control devices mediates data transfer control between a plurality of terminal devices and a host data processing device, and In the data transmission control system, each of the terminal control devices interrupts the host data processing device in response to data reception from the terminal device and notifies the host data processing device of processing, wherein the at least one terminal control device The device divides a plurality of terminal devices connected to itself into a plurality of groups, has one terminal interface circuit section for each group, and processes data in a plurality of terminal interface circuit sections corresponding to each group. The present invention is characterized in that, when data reception occurs, the data received by each of the plurality of terminal interface circuits are combined into one and an interrupt is applied to the host data processing device. This will be explained below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of a data transmission control system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of a terminal control device used in the present invention. In FIG. 1, 1 is a host data processing unit, 2-1 and 2-2 are terminal control units TCU, and 3
1 to 3-n and 4-1 to 4-m represent terminal devices, respectively.

The illustrated terminal control devices 2-1 and 2-2 each have, for example, a number of 10
It controls up to several hundred terminal devices and mediates data transmission between the host data processing device 1 and each terminal device.

In the case of the present invention, as shown in FIG. 2 showing an embodiment of the configuration of a terminal control device 21, data received from a plurality of terminal devices are collected into one data as much as possible and notified to the host data processing device 1. I have to.

In FIG. 2, 5 is the main controller, 6-1 to 6-3
are terminal interface circuit sections, 7-1 to 7-3, respectively.
are start flag registers that turn on when receiving data from the terminal device 5, and 8-
1 to 8-3 are receive flag registers, which are turned on when all data from the terminal device is received and stored in the section memory SM, and 9-1 to 9-3 are transmission flag registers, respectively.・Flags・ 4 registers that turn on when the response data from the host data processing device has been sent to the terminal device, 10
-1 to 10-3 are section memories each having a section corresponding to each terminal device and temporarily storing data; 11 is a first timer; 12-1 and 12-2 are respectively host-side interfaces; Ace circuit section 13 is a check circuit section which monitors the processing status regarding each terminal interface circuit section 6-1 to 6-3; 14 is a second check circuit section;
15 to 20 represent AND circuits, and 21 represents an OR circuit. As shown in the figure, one terminal control device 2
-1, when n terminal devices are connected to n
For example, three terminal interface circuit units TiC capable of performing interface processing with the terminal devices are provided, and the n terminal devices are divided into groups of (n/3) devices each. A terminal interface circuit section 6- that can perform interface processing with the n terminal devices for each terminal device.
Make 1, 6-2, 6-3.

The terminal control device 2-1 shown in FIG. 2 operates as follows. That is, (1) it is assumed that the host data processing device 1 instructs the main controller 5 to start operation via the interface circuit section 12-1.

(2) The main controller 5 sets a predetermined monitoring time in the first timer 11, and each terminal interface circuit unit 6-1, 6
-2 and 6-3 are commanded to receive data.

(3) Each terminal interface circuit section 6-1 to 6-3
start receiving data completely independently and in parallel.

(4) Each terminal interface circuit section 6-1 to 6-3
When each starts receiving data from a terminal device, it sets start flag registers SF7-1 to 7-3, and when data reception is completed, it sets receive flag registers RF8-1 to RF8-3.

(5) After issuing the data reception command to the terminal interface circuit units 6-1 to 6-3, the main controller 5 sends the first
wait for a timer interrupt from timer 11.

(6) In response to timer interrupts, each start flag,
Searches registers J, P, 7 and 3, and if they are all off, sets timer 11 again and waits for the next timer interrupt.

(7) When a timer interrupt occurs, if any start flag register SF7-1 to SF7-3 is on, that start flag register S
Wait until the receive flag register RF corresponding to F turns on. (8) Receive flag register R
When F is turned on, the main controller 5 interrupts the host data processing device 1 via, for example, the host-side interface circuit section 12-1, and receives a read command from the host data processing device 1. When issued, at that point, each data set in the section memories SMIO-1 to 10-3 is transferred to the host data processing device 1 all at once. (9) Host data processing device 1
After executing the processing related to the data transferred in bulk, it creates response data and sends it to the interface circuit section 1.
2-1, the response data is transferred all at once in response to a write command, and the interface circuit section 12-1 stores it in the corresponding section memories SMIO-1 to 10-3.

When the storage is completed, the main controller 5 is notified of this fact. (To) In response, the main controller 5 instructs the terminal interface circuit units 6-1 to 6-3 to transmit data.

(11) Each terminal interface circuit section 6-1 to 63
is the corresponding receipt flag register RF8-
1 to 8-3 are on, the response data in the section memories SMIO-1 to 10-3 is sent to the terminal device, and upon completion, transmission flag registers TF9-1 to TF9- are sent. 3 to notify the main controller 5.

(12) When the transmission flag registers TF9-1 to TF9-3, which correspond to the ON states of the receive flag registers RF8-1 to RF8-3, respectively, turn on, the main controller 5 controls the terminal interface. Circuit section 6-
1 to 6-3, cancel the data transmission command and register each register.
Clear J, P or 7-3, 8-1 or 8-3, 9-1 or 9-3.

Next, the main controller 5 sets a predetermined monitoring time in the timer 11, and the terminal interface circuit units 6-1 to 6-6
Issue a data reception command to -3 and execute it repeatedly thereafter.

In the above, 3 is used as the terminal interface circuit section TiC.
However, the amount of traffic and the TiC of the relevant circuit are
By appropriately selecting the number of terminals and the time set to the timer 11, it becomes possible to combine the received data from a plurality of terminal devices into one and notify the host data processing device.

By employing the above configuration, the number of interrupts to the host data processing device can be reduced and the overhead can be substantially reduced, but this raises the following problem.

That is, in the conventional case (when there is only one terminal interface circuit unit TiC), even if a failure occurred during one data transmission, it was possible to identify which terminal the failure was for. . However, when adopting the configuration of the present invention, data from a plurality of terminal devices is collectively controlled, making it impossible to identify failures in individual terminal devices. For this purpose, in the case shown in FIG. 2, a check circuit section 13 for fault monitoring is provided to control fault detection.

That is, a start flag register SFl, a receive flag register RFl, and a transmission flag register T correspond to each terminal interface circuit section.
During normal operation, F repeats the sequence of SF on → RF on → TF on → SF, RF, TF off.

Although it is impossible to predict when a failure will occur, the most preferable way to identify which terminal device the failure is caused by is the receive flag register RF.
After the above transmission flag is turned on,
This is to monitor the time until the register TF turns on. This is because during this time, the host data processing device appears to be processing data from the terminal device, and the terminal device is not receiving any response data and is therefore not performing any operations. Therefore, the check circuit section 13 monitors whether the transmission flag register TF turns on within a predetermined time after the receive flag register RF turns on. That is, when any one of the receive flag registers SF8-1 to SF83 is turned on, the check circuit section 13 causes the timer 14 to transmit the transmission signal.
Set the maximum time that flag register TF will be on and wait for an interrupt from timer 14.

At this point, the transmission flag register TF
If it is turned on, it means that the process was performed normally, so the timer 14 is cleared. If any one of the transmission flag registers TF corresponding to the ON state of the receive flag register RF remains OFF at the time of an interrupt from the timer 14, it is assumed that a failure has occurred in the processing and the host The data processing device 1 is notified of the situation. Needless to say, the host data processing device 1 executes correction processing for the previous processing. As described above, according to the present invention, since a plurality of data receptions are collectively notified to the host data processing device, overall overhead is reduced.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of a data transmission control system to which the present invention is applied, and FIG. 2 shows the configuration of an embodiment of a terminal control device used in the present invention. In the figure, 1 is a host data processing device, 2-1 and 2-2 are terminal control devices, 3 and 4 are terminal devices, 5 is a main control device, and 6-1, 6-2, and 6-3 are terminal control devices. 11 represents a first timer, 13 represents a check circuit, and 14 represents a second timer, respectively.

Claims (1)

[Claims] 1. Each of one or more terminal control devices mediates data transfer control between a plurality of terminal devices and a host data processing device, and receives data from the terminal devices. In a data transmission control system in which each of the terminal control devices correspondingly interrupts the host data processing device and notifies the host data processing device of processing, the at least one terminal control device is connected to itself. A plurality of terminal devices are divided into a plurality of groups, and one terminal interface circuit section is provided for each group, and when data reception occurs in the plurality of terminal interface circuit sections corresponding to each of the above groups, each of the plurality of terminal devices is divided into a plurality of groups. 1. A control method for a terminal control device, characterized in that the data received by each terminal interface circuit section are combined into one and an interrupt is applied to the host data processing device. 2. The at least one terminal control device includes a check circuit unit that individually monitors processes related to the terminal interface circuit units corresponding to each of the plurality of sets, and the check circuit unit individually monitors each process corresponding to the one interrupt. 2. A control system for a terminal control device according to claim 1, wherein processing related to the terminal interface circuit is monitored and the host data processing device is notified when a failure occurs.