JPS5931259B2 - Soushinyutsuriyokuseigiyokairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission output control circuit for suppressing transmission at frequencies other than channels used in a transceiver.

An object of the present invention is to prevent radio interference caused by the oscillation frequency in the unlocked state being different from the frequency in the locked state in a transmitter/receiver incorporating a phase-locked frequency synthesizer.

A further object of the present invention is to keep the transmission output control conditions constant especially when the phase-locked loop conditions deviate from the designed values due to variations in the circuit elements used.

Alternatively, the transmission output control conditions may be changed for devices with different conditions such as frequency tolerance for the same type of phase-locked loop. In general, for wireless transceivers that use radio waves, there are detailed regulations regarding the frequency used, output wattage, spurious emissions, and other transmission outputs, but these are well known. For example, the carrier wave for each channel (27MHZ band) in an American citizen band transmitter/receiver is:
Since the channel spacing is set to IOKHZ or 5KHZ, at least the frequency deviation must be less than 0.01%.

Conventionally, multi-channel transceivers for citizen bands have used crystal oscillators corresponding to the number of channels as oscillation sources with small frequency deviations in order to obtain the frequency of each channel. Alternatively, each channel frequency was synthesized by combining multiple crystal oscillators. Therefore, for devices with a very large number of channels,
The number of crystal oscillators increases proportionally, and especially when the number of channels reaches several tens and the channel spacing is selected as small as 5 KHz, extremely high precision crystal is required for the oscillator. The costs involved were high. Furthermore, in order to obtain the frequency of each channel, the resonator crystal to be used must be selectively switched from among a large number of resonators, making the channel changeover switch circuit complicated. On the other hand, as shown in Figure 1, a phase-locked loop frequency synthesizer with one reference frequency source and a digital counter that can set a variable frequency oscillator to an arbitrary frequency with respect to the reference frequency is used as the channel frequency source of the transmitter/receiver. If used, if there is one crystal with a small deviation as the reference frequency, it is possible to synthesize channel frequencies with almost the same accuracy as the reference frequency, and the number of channels and channel spacing require a digital counter for setting in advance. If it is designed to have a variable range, it becomes possible to synthesize all channel frequencies with one synthesizer.

Figure 1 is a block diagram of a phase lock type synthesizer, where 1 is a reference frequency oscillator, 2 is a counter,
3 is a program counter for setting a frequency, 6 is a phase comparator, 9 is a charge pump, and 10 is a variable frequency oscillator restriction circuit, which usually consists of an integrator (filtering circuit). 10 is a variable frequency oscillator that oscillates at a frequency set by the program counter 3 based on the output of 9, and is usually a voltage controlled oscillator.

In the phase lock loop type frequency synthesizer, the oscillation frequency of the variable frequency oscillator 11 is in a controlled state by the loop (hereinafter referred to as a locked state) and in an uncontrolled state (non-locked state). is possible.

The non-lock state is when the power is first turned on, when the program counter 3 is reset to a different wave number, or when the lock is lost due to a disturbance. In this case, the variable frequency oscillator oscillates irregularly within the variable frequency range of the oscillator input. Normally, oscillation occurs at the upper or lower limit of the input variable range. When using a phase lock type frequency synthesizer for the channel frequency of a transmitter/receiver, especially when using the synthesizer output directly or indirectly as a transmission carrier wave, the above oscillation frequency in the unlocked state is the oscillation frequency in the locked state, that is, the desired frequency. Since the frequency does not match, the number of channels used can not be obtained. At this time, there is a good possibility that the transmitted signal is related to a channel or other band, and it cannot be received by the receiving device of the other party, and may also become an interference radio wave for other communications. The present invention eliminates such problems when using a phase lock loop type frequency synthesizer in a transmitter/receiver, and improves the performance of a transmitter/receiver using a phase lock type synthesizer by stopping unnecessary radio waves.

FIG. 2, FIG. 3, and FIG. 4 are examples of the transmission control circuit in an unlocked state, which is the present invention. Assume that the channel frequency interval is 10 KHZ, and in the phase converter shown in FIG. 1, the reference frequency and the frequency of the variable oscillation circuit 11 are set to 10 KHZ to match the channel frequency interval.

In this case, counter 2 sets the frequency of reference oscillator 1 to 10K
It is a fixed counter for stepping down to HZ, and the counter 3 is a program counter that can be preset so that 10 KHz is obtained as the final output 5 when the variable oscillator 11 is oscillating at the expected frequency. The output of the phase comparator 6 is naturally a 10KH2S pulse train. 7 is a signal for detecting the amount of phase advance of the output 5 of the program counter 3 with respect to the output 4 of the reference frequency counter.

8 is a signal for detecting a phase delay amount of 5 relative to 4.

For the following explanation, the output of the phase comparator is as follows. (1) Locked in an ideal state.

When output 4 of counter 2 and output 5 of program counter 3 have completely the same frequency and the phase difference is 0.

At this time, no signal is output from the outputs 7 and 8 of the phase comparator 6. (2) Practically in a locked state.

(The frequencies of 4 and 5 match perfectly, and the phase difference is constant.

Alternatively, the oscillation frequency of the variable oscillator due to vibration based on the loop transfer function varies within the tolerance of the preset frequency, and the phase difference varies slightly. (3) Unlocked.

The oscillation frequency of the variable oscillator 11 is outside the permissible deviation from the preset frequency.

In the phase lock loop shown in Fig. 1, when the charge pump 9 and the integrator 10 are implemented as a circuit, leakage current always occurs. Since the state cannot be maintained forever, (1) is difficult to achieve, (2),
(3) has the so-called locked state and non-locked state mentioned in this description.

FIG. 5 20 shows the waveform of the charge pump output 9 when it is in a practically locked state and is slightly vibrating.

The pulse interval is 10 KHz, and as the phase difference changes to 10 or 1 around O, minute pulses are generated above and below a certain voltage V. 21 in FIG. 5 represents the output waveform of the charge pump 9 in the unlocked state, and 22 represents the waveform in FIG. 2 12 at this time. Figures 3 and 4 are
This is an example of a transmission output control circuit according to the present invention.

In FIG. 3, when the NOR circuit output 12 of FIG. 2 is applied to the middle 13 of two directly connected diodes by AC coupling, the waveform of 12 becomes a minute pulse as shown in FIG. 5, 20. In the component state, the values of the base resistance and capacitor are set so that the potential of the base 14 of the transistor keeps the transistor in a completely ON state.

At this time, the synthesizer loop is in a locked state and the transistor is in an ON state. The loop becomes unlocked and
When the waveform of No. 12 becomes the waveform shown in FIG. 5, the signal No. 12 changes with an amplitude of Vcc and a wide pulse width, so the potential of the base 14 is reverse biased with respect to the emitter of the transistor 0FF. state.

In FIG. 4, outputs of opposite polarity are obtained for the same signal input 12. The base 18 of the transistor is at 0V in the locked state and near +0.7V in the unlocked state.
FIG. 5 23 shows an example of the output waveform of the charge pump 9 when the lock state changes to the non-lock state.
The waveform in FIG. 12 changes as shown in 24, and the waveform in 19 changes as shown in 25. Here, the diode 26 plays the role of keeping 17 at the GND level, and when the signal 12 changes from +Vcc to 0V, charge flows from the AC coupling capacitor GND through the diode 26 and is charged. Conversely, when the voltage 12 changes from 0V to +Vcc, the charge charged in the AC coupling capacitor is discharged through the diode 27, charged into the capacitor 28, and further flows into the emitter through the base of the transistor. The transistor maintains a substantially ON state until the charge stored in the capacitor 28 is discharged through the base to the emitter. Here, as shown in FIG. 3 or FIG. 4, it is extremely important to construct a diode rectifier circuit because the input signal is a pulse train. If 24 waveforms are CR integrated and applied to the transistor base to determine ON or OFF, the CR time constant must be sufficiently large (several tens to hundreds of pulses) relative to the pulse interval. When the lock state changes to the non-lock state, there is a delay of several tens to hundreds of pulses before an inversion appears in the transistor output.

On the other hand, in the circuit shown in Figure 3 or 4, it is sufficiently possible to invert the transistor output with a delay of at most a few pulses after changing to the non-lock state, and the degree of delay depends on the capacitance of the AC coupling capacitor. It is clear that it can be set arbitrarily by When using the output of the variable frequency oscillator 11 directly or indirectly as a transmission carrier wave, in an unlocked state, not only the carrier frequency of the channel to be used is not obtained, but also
Since there is a possibility that interference radio waves from other channels or other bands are being generated, in order to stop unnecessary radio waves, the transmitting signal must be immediately stopped when the lock state changes to the non-lock state.

Therefore, as mentioned above, it is important to immediately detect an unlocked state using the diode rectifier circuit. On the other hand, when changing from an unlocked state to a locked state, it is necessary to send out a transmission signal, but even if the delay at this time were several hundred pulses, there would be no practical problem. FIG. 4 is an example of stopping the transmission signal in an unlocked state by lowering the base bias of one amplification stage of the transmission signal to GND. FIGS. 6 and 7 are examples of circuits in which the operating conditions of the transistor can be arbitrarily set for the cases shown in FIGS. 3 and 4.

Either one of 27 or 28 in FIG. 7 may be a variable resistor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase lock type frequency synthesizer.

Claims (1)

[Claims] 1. In a transmitter/receiver having a phase-locked frequency synthesizer, means for synthesizing phase lead and phase lag detection signals of a phase comparator of the synthesizer to form a unipolar phase detection pulse train; inputting the pulse train to an integrating circuit constituted by a diode, inputting the output of the integrating circuit to the base or gate of a transistor,
A transmission output control circuit, characterized in that the transmission output is stopped when the synthesizer is in an unlocked region by turning on or off the transistor according to the pulse train. 2. The transmission output control circuit according to claim 1, wherein the integrating circuit includes a variable resistance element, and the non-lock region level can be set by adjusting the variable resistance element. control circuit.